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Abstract
A new approach to an analog ultra-low power visionchip design is presented. The prototype chip performs low-levelconvolutional image processing algorithms in real time. Thecircuit is implemented in 0.35 μm CMOS technology, contains64 x 64 SIMD matrix with embedded analogue processors APE(Analogue Processing Element). The photo-sensitive-matrix is of2.2 μm x 2.2 μm size, giving the density of 877 processors permm2. The matrix dissipates less than 0.4 mW (less than 0.1 μWper processor) of power under 3.3 V supply, and their imageprocessing speed is up to 100 frames/s.
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- Category:
- Conference activity
- Type:
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Title of issue:
- 20th European Conference on Circuits Theory and Design ECCTD 2011,Linkoping, Szwecja, 2011. - [pendrive] strony 745 - 748
- Language:
- English
- Publication year:
- 2011
- Bibliographic description:
- Jendernalik W., Jakusz J., Blakiewicz G., Piotrowski R., Szczepański S.: Analog CMOS processor for early vision processing with highly reduced power consumption// 20th European Conference on Circuits Theory and Design ECCTD 2011,Linkoping, Szwecja, 2011. - [pendrive]/ : , 2011, s.745-748
- DOI:
- Digital Object Identifier (open in new tab) 10.1109/ecctd.2011.6043651
- Verified by:
- Gdańsk University of Technology
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