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RNS/TCS CONVERTER DESIGN USING HIGH-LEVEL SYNTHESIS IN FPGA

Abstract

An experimental high-level synthesis (HLS) of the residue number system (RNS) to two’s-complement system (TCS) converter in the Vivado Xilinx FPGA environment is shown. The assumed approach makes use of the Chinese Remainder Theorem I (CRT I). The HLS simplifies and accelerates the design and implementation process, moreover the HLS synthesized architecture requires less hardware by about 20% but the operational frequency is smaller by 30% than that for the VHDL designed converter.

Details

Category:
Magazine publication
Type:
artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
Published in:
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej pages 121 - 125,
ISSN: 2353-1290
Language:
English
Publication year:
2017
Bibliographic description:
Smyk R., Czyżak M.: RNS/TCS CONVERTER DESIGN USING HIGH-LEVEL SYNTHESIS IN FPGA// Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej. -., nr. 57 (2017), s.121-125
Sources of funding:
  • Działalność statusowa
Verification:
Gdańsk University of Technology

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