Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path

Waldemar Jendernalik; Jacek Jakusz; Robert Piotr Piotrowski; Grzegorz Blakiewicz; Stanisław Szczepański

doi:10.3390/electronics10141613

Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path

Abstract

A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 m2), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).

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Authors (5)

Waldemar Jendernalik dr hab. inż.
Jacek Jakusz dr hab. inż.
Robert Piotr Piotrowski
Grzegorz Blakiewicz dr hab. inż.
Stanisław Szczepański prof. dr hab. inż.

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DOI:: Digital Object Identifier (open in new tab) 10.3390/electronics10141613
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Category:

Articles

Type:

artykuły w czasopismach

Published in:

Electronics no. 10,
ISSN: 2079-9292

Language:

English

Publication year:

2021

Bibliographic description:

Jendernalik W., Jakusz J., Piotrowski R. P., Blakiewicz G., Szczepański S.: Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path// Electronics -Vol. 10,iss. 14 (2021), s.1613-

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