FPGA implementation of the multiplication operation in multiple-precision arithmetic

Kamil Rudnicki; Tomasz Stefański

doi:10.23919/mixdes.2017.8005214

FPGA implementation of the multiplication operation in multiple-precision arithmetic

Abstrakt

Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing systems allows one to implement MPA algorithms in hardware. Whereas addition and subtraction operations of two n-digit numbers require O(n) operations, the basecase multiplication is equivalent to the convolution computation that requires O(n2) operations. Therefore, an efficient implementation of the multiplication operation is crucial for application of the reconfigurable hardware in MPA computations. In this contribution, our implementation of the base case-multiplication algorithm in MPA on FPGA is presented. The method is implemented using the very high speed integrated circuit hardware description language (VHDL) and benchmarked on Xilinx Artix-7 FPGA. In the developed implementation of the MPA multiplication, the multiplication of two integer 1024-bit numbers (2048-bit numbers) takes 205 nsec (819 nsec) with the use of 40 DSP modules. It gives two-fold speedup in comparison to the reference results published in the literature. The developed digital circuit of the MPA multiplier works with integer numbers of precision varying in the range between 16 bits and 32 kbits. Such a scalability allows one to use the developed method not only in scientific computing, but also in embedded systems employing encryption based on MPA.

Cytowania

4

CrossRef
0

Web of Science
5

Scopus

Autorzy (2)

Kamil Rudnicki dr
Tomasz Stefański dr hab. inż.

Cytuj jako

Pełna treść

pobierz publikację

pobrano 1286 razy

Wersja publikacji: Accepted albo Published Version
Licencja: Copyright (2017 by Department of Microelectronics & Computer Science, Lodz University of Technology)

Słowa kluczowe

MULTIPLE PRECISION ARITHMETIC, FPGA

Informacje szczegółowe

Kategoria:: Aktywność konferencyjna
Typ:: publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
Tytuł wydania:: Proceedings of the 24th International Conference “Mixed Design of Integrated Circuits and Systems” strony 271 - 275
Język:: angielski
Rok wydania:: 2017
Opis bibliograficzny:: Rudnicki K., Stefański T.: FPGA implementation of the multiplication operation in multiple-precision arithmetic// Proceedings of the 24th International Conference “Mixed Design of Integrated Circuits and Systems”/ ed. Andrzej Napieralski Łódź: , 2017, s.271-275
DOI:: Cyfrowy identyfikator dokumentu elektronicznego (otwiera się w nowej karcie) 10.23919/mixdes.2017.8005214
Weryfikacja:: Politechnika Gdańska