A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs - Publikacja - MOST Wiedzy

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A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs

Abstrakt

In this brief, a power-efficient digital technique for gain and offset correction in slope analog-to-digital converters (ADCs) has been proposed. The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by a specially prepared clock-enable pulse sequence. This brief describes the properties of ADCs utilizing this clock stopping technique, including power dissipation, integral, and differential nonlinearity. The experimental validation has been performed for the ASIC implementation of the 128-pixel imager containing photo-sensors integrated with ADCs. Finally, a modification is proposed that increases the accuracy of the gain correction. Measurements confirm functionality of the proposed approach. Reduction of the PRNU (to ~0.4 LSB) has been achieved as well.

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Informacje szczegółowe

Kategoria:
Publikacja w czasopiśmie
Typ:
artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
Opublikowano w:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS nr 67, strony 979 - 983,
ISSN: 1549-7747
Język:
angielski
Rok wydania:
2020
Opis bibliograficzny:
Kłosowski M.: A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs// IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS. -Vol. 67., iss. 6 (2020), s.979-983
DOI:
Cyfrowy identyfikator dokumentu elektronicznego (otwiera się w nowej karcie) 10.1109/tcsii.2019.2928183
Źródła finansowania:
Weryfikacja:
Politechnika Gdańska

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