Wyszukiwarka
Abstrakt
Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing systems allows one to implement MPA algorithms in hardware. Whereas addition and subtraction operations of two n-digit numbers require O(n) operations, the basecase multiplication is equivalent to the convolution computation that requires O(n2) operations. Therefore, an efficient implementation of the multiplication operation is crucial for application of the reconfigurable hardware in MPA computations. In this contribution, our implementation of the base case-multiplication algorithm in MPA on FPGA is presented. The method is implemented using the very high speed integrated circuit hardware description language (VHDL) and benchmarked on Xilinx Artix-7 FPGA. In the developed implementation of the MPA multiplication, the multiplication of two integer 1024-bit numbers (2048-bit numbers) takes 205 nsec (819 nsec) with the use of 40 DSP modules. It gives two-fold speedup in comparison to the reference results published in the literature. The developed digital circuit of the MPA multiplier works with integer numbers of precision varying in the range between 16 bits and 32 kbits. Such a scalability allows one to use the developed method not only in scientific computing, but also in embedded systems employing encryption based on MPA.
Cytowania
-
4
CrossRef
-
0
Web of Science
-
5
Scopus
Autorzy (2)
-
Kamil Rudnicki dr
Cytuj jako
Pełna treść
- Wersja publikacji
- Accepted albo Published Version
- Licencja
- Copyright (2017 by Department of Microelectronics & Computer Science, Lodz University of Technology)
Słowa kluczowe
Informacje szczegółowe
- Kategoria:
- Aktywność konferencyjna
- Typ:
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Tytuł wydania:
- Proceedings of the 24th International Conference “Mixed Design of Integrated Circuits and Systems” strony 271 - 275
- Język:
- angielski
- Rok wydania:
- 2017
- Opis bibliograficzny:
- Rudnicki K., Stefański T.: FPGA implementation of the multiplication operation in multiple-precision arithmetic// Proceedings of the 24th International Conference “Mixed Design of Integrated Circuits and Systems”/ ed. Andrzej Napieralski Łódź: , 2017, s.271-275
- DOI:
- Cyfrowy identyfikator dokumentu elektronicznego (otwiera się w nowej karcie) 10.23919/mixdes.2017.8005214
- Bibliografia: test
-
więcej (18) mniej
- D. H. Bailey, "High-precision floating-point arithmetic in scientific computation," Comput. Sci. Eng., vol. 7, no. 3, pp. 54-61, 2005. otwiera się w nowej karcie
- D. H. Bailey, R. Barrio and J. M. Borwein, "High-precision computation: Mathematical physics and dynamics," Appl. Math. Comput., vol. 218, no. 20, pp. 10106-10121, 2012. otwiera się w nowej karcie
- T. P. Stefanski, "Electromagnetic problems requiring high-precision computations," IEEE Antennas Propag. Mag., vol. 55, no. 2, pp. 344- 353, 2013. otwiera się w nowej karcie
- A. Karatsuba and Y. Ofman, "Multiplication of many-digital numbers by automatic computers," Proceedings of the USSR Academy of Sciences, vol. 145, pp. 293-294, 1962. otwiera się w nowej karcie
- D. E. Knuth, The Art of Computer Programming, Volume 2 (3rd Ed.): Seminumerical Algorithms., Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1997.
- A. Schönhage and V. Strassen, "Schnelle multiplikation grosser zahlen," Computing, vol. 7, no. 3, pp. 281-292, 1971. otwiera się w nowej karcie
- T. Granlund, "The GNU multiple precision arithmetic library (Edi- tion 6.1.2)," GMP Development Team, 2016 [Online]. Available: www.gmplib.org
- SDAccel Platform Reference Design User Guide -Developer Board for Acceleration with KU115, UG1234 (v2016.3) November 30, 2016 [Online]. Available: www.xilinx.com otwiera się w nowej karcie
- Series FPGAs Data Sheet: Overview -Product Specification, DS180 (v2.2) December 15, 2016 [Online]. Available: www.xilinx.com otwiera się w nowej karcie
- Y. Lei, Y. Dou, S. Guo, J. Zhou, "FPGA implementation of variable- precision floating-point arithmetic," in: O. Temam, PC. Yew, B. Zang (eds) Advanced Parallel Processing Technologies. APPT 2011. Lecture Notes in Computer Science, vol. 6965, Springer, Berlin, Heidelberg, 2011. otwiera się w nowej karcie
- R. L. Rivest, A. Shamir and L. Adleman, "A method for obtaining digital signatures and public-key cryptosystems," Commun. ACM, vol. 21, no. 2, pp. 120-126, 1978. otwiera się w nowej karcie
- J. Daemen, V. Rijmen, The Design of Rijndael: AES -The Advanced Encryption Standard., Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2002. otwiera się w nowej karcie
- A. Kalathungal, An Arbitrary Precision Integer Arithmetic Library for FPGAs., MSc thesis, University of Cincinnati, OH, USA, 2013.
- IBM, System z9 Enterprise Class, System Overview, April 2009 [On- line]. Available: www-01.ibm.com otwiera się w nowej karcie
- Vivado Design Suite User Guide -Getting Started, UG910 (v2016.3) October 5, 2016 [Online]. Available: www.xilinx.com otwiera się w nowej karcie
- Series DSP48E1 Slice User Guide, UG479 (v1.9) September 27, 2016 [Online]. Available: www.xilinx.com otwiera się w nowej karcie
- Nexys Video FPGA Board Reference Manual, Revised May 4, 2016 [Online]. Available: www.digilentinc.com otwiera się w nowej karcie
- Virtex-6 Family Overview -Product Specification, DS150 (v2.5) August 20, 2015 [Online]. Available: www.xilinx.com otwiera się w nowej karcie
- Weryfikacja:
- Politechnika Gdańska
wyświetlono 125 razy
Publikacje, które mogą cię zainteresować
Open-Source Coprocessor for Integer Multiple Precision Arithmetic
- K. Rudnicki,
- T. Stefański,
- W. Żebrowski