Implementation of multi-operand addition in FPGA using high-level synthesis
The paper presents the results of high-level synthesis (HLS) of multi-operand adders in FPGA using the Vivado Xilinx environment. The aim was to estimate the hardware amount and latency of adders described in C-code. The main task of the presented experiments was to compare the implementations of the carry-save adder (CSA) type multi-operand adders obtained as the effect of the HLS synthesis and those based on the basic component being 4-operand adder with fast carry-chain available in FPGA’s implemented in Verilog. However, the HLS synthesis simplifies the design and prototyping process but the received results indicate that the circuit obtained as the result of such synthesis requires twice more resources and is slower than its counterpart design using Verilog.
Robert Smyk, Maciej Czyżak. (2018). Implementation of multi-operand addition in FPGA using high-level synthesis, (2), 170-173. https://doi.org/10.15199/48.2018.02.39
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