Space Vector Pulsewidth Modulation Strategy for Multilevel Cascaded H-Bridge Inverter With DC-Link Voltage Balancing Ability - Publikacja - MOST Wiedzy

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Space Vector Pulsewidth Modulation Strategy for Multilevel Cascaded H-Bridge Inverter With DC-Link Voltage Balancing Ability

Abstrakt

Space vector pulsewidth modulation (SVPWM) algorithms for cascaded H-bridge multilevel (CHB ML) inverter usually provide the possibility of using several combinations of active voltage vectors to generate the same output voltage vector. For preselected H-bridges, some of them may generate output voltages opposite to the assumed direction. This results in the change of the dc-link voltages of these H-bridges in the opposite direction to the assumed direction in the ordering algorithm. Consequently, these algorithms are characterized by undue constraints and narrow possibilities of dc-link voltage balancing. In the proposed control algorithm, CHB ML inverter is treated as groups of successively activated three-level inverters; depending on the length of the reference voltage vector. These three-level inverters consist of three H-bridges selected from each phase. The proposed extended selection method enables firm-grip control of the dc-link voltages. For a given direction of phase currents, the possibility of using H-bridges with lowest and highest dc-link voltages is simultaneously analyzed. Additionally, each of the three-level inverters is controlled by one of three proposed alternative modulation methods for which both the attainable output voltage vectors and unbalanced dc-link voltages are predicted. Simulation and experimental results confirm the correctness of the algorithm execution.

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Informacje szczegółowe

Kategoria:
Publikacja w czasopiśmie
Typ:
artykuły w czasopismach
Opublikowano w:
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS nr 70, strony 1161 - 1170,
ISSN: 0278-0046
Język:
angielski
Rok wydania:
2023
Opis bibliograficzny:
Lewicki A., Odeh C., Morawiec M.: Space Vector Pulsewidth Modulation Strategy for Multilevel Cascaded H-Bridge Inverter With DC-Link Voltage Balancing Ability// IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS -Vol. 70,iss. 2 (2023), s.1161-1170
DOI:
Cyfrowy identyfikator dokumentu elektronicznego (otwiera się w nowej karcie) 10.1109/tie.2022.3158005
Weryfikacja:
Politechnika Gdańska

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