An architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length...

A scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues...

In this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System (MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue reprezentation of scaled terms, binary addition of these representations...