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Abstract
The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms ispresented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated usinga 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 framesper second, or achieve very low power consumption, several μW. Finally, the experimental results are presented and discussed.
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- DOI:
- Digital Object Identifier (open in new tab) 10.2478/v10175-011-0018-x
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- Category:
- Articles
- Type:
- artykuł w czasopiśmie wyróżnionym w JCR
- Published in:
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Bulletin of the Polish Academy of Sciences-Technical Sciences
no. 59,
pages 141 - 147,
ISSN: 0239-7528 - Language:
- English
- Publication year:
- 2011
- Bibliographic description:
- Jendernalik W., Jakusz J., Blakiewicz G., Piotrowski R. P.: CMOS realisation of analogue processor for early vision processing// Bulletin of the Polish Academy of Sciences-Technical Sciences. -Vol. 59, iss. nr 2 (2011), s.141-147
- DOI:
- Digital Object Identifier (open in new tab) 10.2478/v10175-011-0018-x
- Verified by:
- Gdańsk University of Technology
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