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Abstract
In this paper we build on our previously proposed MPI I/O NVRAM distributed cache for high performance computing. In each cluster node it incorporates NVRAMs which are used as an intermediate cache layer between an application and a file for fast read/write operations supported through wrappers of MPI I/O functions. In this paper we propose optimizations of the solution including handling of write requests with a synchronous mode, additional modes preventing data preloading from a file and synchronization on file close if the solution is used as temporary cache only. Furthermore, we have evaluated the solution for a real application that computes powers of an adjacency matrix of a graph in parallel. We demonstrated superiority of our solution compared to a regular MPI I/O implementation for various powers and numbers of graph nodes. Finally, we presented good scalability of the solution for more than 600 processes running on a large HPC cluster.
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- Category:
- Conference activity
- Type:
- materiały konferencyjne indeksowane w Web of Science
- Title of issue:
- Computer Information Systems and Industrial Management strony 15 - 26
- Language:
- English
- Publication year:
- 2017
- Bibliographic description:
- Malinowski A., Czarnul P..: Distributed NVRAM Cache – Optimization and Evaluation with Power of Adjacency Matrix, W: Computer Information Systems and Industrial Management, 2017, ,.
- DOI:
- Digital Object Identifier (open in new tab) 10.1007/978-3-319-59105-6_2
- Verified by:
- Gdańsk University of Technology
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