Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Waldemar Jendernalik; Jacek Jakusz; Grzegorz Blakiewicz

doi:10.3390/electronics10232931

Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Abstract

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for uffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).

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DOI:: Digital Object Identifier (open in new tab) 10.3390/electronics10232931
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Articles

Type:

artykuły w czasopismach

Published in:

Electronics no. 10,
ISSN: 2079-9292

Language:

English

Publication year:

2021

Bibliographic description:

Jendernalik W., Jakusz J., Blakiewicz G.: Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters// Electronics -Vol. 10,iss. 23 (2021), s.2931-

DOI: