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CMOS sensor with smart grid of pixels of layered structure for fast acquisition and simultaneous extraction of information from image
Details
- Financial Program Name:
- OPUS
- Organization:
- Narodowe Centrum Nauki (NCN) (National Science Centre)
- Agreement:
- UMO-2016/23/B/ST7/03733 z dnia 2017-07-14
- Realisation period:
- 2017-07-14 - 2022-07-13
- Project manager:
- prof. dr hab. inż. Stanisław Szczepański
- Realised in:
- Department of Microelectronic Systems
- Project's value:
- 791 700.00 PLN
- Request type:
- National Research Programmes
- Domestic:
- Domestic project
- Verified by:
- Gdańsk University of Technology
Papers associated with that project
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total: 11
Catalog Projects
Year 2024
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In-ADC, Rank-Order Filter for Digital Pixel Sensors
PublicationThis paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS...
Year 2023
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Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors
PublicationThis brief presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp,...
Year 2022
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Low-Voltage Low-Power Filters with Independent ω0 and Q Tuning for Electronic Cochlea Applications
PublicationAn acoustic second-order low-pass filter is proposed for filter banks emulating the operation of a human cochlea. By using a special filter structure and an innovative quality (Q)-factor tuning technique, an independent change of the cutoff frequency (ω0) and the Q-factor with unchanged gain at low frequencies is achieved in this filter. The techniques applied result in a simple filter design with low Q-factor sensitivity to component...
Year 2021
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Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters
PublicationBuffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more...
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Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors
PublicationThis paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscilla-tors as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip imple-mentation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability...
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Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path
PublicationA voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology,...
Year 2020
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A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces
PublicationThe paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving,...
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A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs
PublicationIn this brief, a power-efficient digital technique for gain and offset correction in slope analog-to-digital converters (ADCs) has been proposed. The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by...
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Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
PublicationIn the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated...
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Hybrid‐mode single‐slope ADC with improved linearity and reduced conversion time for CMOS image sensors
PublicationIn the paper, a single‐slope analog‐to‐digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid‐mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single‐slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion...
Year 2018
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A High-Efficient Measurement System With Optimization Feature for Prototype CMOS Image Sensors
PublicationIn this paper, a gray-scale CMOS image sensor (CIS) characterization system with an optimization feature has been proposed. By using a very fast and precise control of light intensity, based on the pulsewidth-modulation method, it is avoided to measure the illuminance every time. These features accelerate the multicriteria CIS optimization requiring many thousands of measurements. The system throughput is 2.5 Gb/s, which allows...
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