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Abstract
This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.
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Authors (6)
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Yichuang Sun
- School of Engineering and Computer Science, University of Hertfordshire, Hatfield, U.K
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Full text
- Publication version
- Accepted or Published Version
- DOI:
- Digital Object Identifier (open in new tab) 10.3390/electronics13010046
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Details
- Category:
- Articles
- Type:
- artykuły w czasopismach
- Published in:
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Electronics
no. 13,
ISSN: 2079-9292 - Language:
- English
- Publication year:
- 2024
- Bibliographic description:
- Kłosowski M., Sun Y., Jendernalik W., Blakiewicz G., Jakusz J., Szczepański S.: In-ADC, Rank-Order Filter for Digital Pixel Sensors// Electronics -Vol. 13,iss. 1 (2024), s.46-
- DOI:
- Digital Object Identifier (open in new tab) 10.3390/electronics13010046
- Sources of funding:
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- Statutory activity/subsidy
- Project CMOS sensor with smart grid of pixels of layered structure for fast acquisition and simultaneous extraction of information from image
- Verified by:
- Gdańsk University of Technology
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