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Abstract
While many scientific, large-scale applications are data-intensive, fast and efficient I/O operations have become of key importance for HPC environments. We propose an MPI I/O extension based on in-system distributed cache with data located in Non-volatile Random Access Memory (NVRAM) available in each cluster node. The presented architecture makes effective use of NVRAM properties such as persistence and byte-level access behind the MPI I/O API. Another advantage of the proposed solution is making development of a parallel application easy and efficient as a programmer just needs to use the well known MPI I/O data model and API while efficient file access is automatically provided without a need for application level optimizations like avoiding frequent operations on a small data. Results of experiments obtained with three different applications suggest, that the extension significantly reduces file access time, especially for small I/O operations. By locating cache facilities on computing nodes, the extension decreases load of file system servers and makes I/O scalable
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Authors (7)
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Krzysztof Czuryło
- Intel Technology Poland .
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Łukasz Dorau
- Intel Technology Poland .
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Maciej Maciejewski
- Intel Technology Poland .
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Paweł Skowron
- Intel Technology Poland .
Cite as
Full text
- Publication version
- Accepted or Published Version
- DOI:
- Digital Object Identifier (open in new tab) 10.15439/2016F52
- License
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Details
- Category:
- Conference activity
- Type:
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Published in:
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Annals of Computer Science and Information Systems
no. 9,
pages 133 - 140,
ISSN: 2300-5963 - Title of issue:
- Position Papers of the 2016 Federated Conference on Computer Science and Information Systems strony 133 - 140
- Language:
- English
- Publication year:
- 2016
- Bibliographic description:
- Malinowski A., Czarnul P., Dorożyński P., Czuryło, K., Dorau, Ł., Maciejewski, M., Skowron P.: A Parallel MPI I/O Solution Supported by Byte-addressable Non-volatile RAM Distributed Cache// Position Papers of the 2016 Federated Conference on Computer Science and Information Systems/ ed. 2016 : , 2016, s.133-140
- DOI:
- Digital Object Identifier (open in new tab) 10.15439/2016f52
- Verified by:
- Gdańsk University of Technology
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