Abstract
In this paper hardware and software realization of direct and inverse AES cryptographic algorithm is presented. Both implementations were made using the Virtex-II FPGA and were practically tested. As the criteria of comparison, the resource utilization, achieved performance and power dissipation were chosen. Hardware realization increases throughput of conversion about 190 times over software implementation and decreases the energy required to process one data packet about 80 times, while resource utilization is about five times greater.
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- Category:
- Articles
- Type:
- artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
- Published in:
-
Zeszyty Naukowe Wydziału ETI Politechniki Gdańskiej. Technologie Informacyjne
no. 14,
pages 589 - 592,
ISSN: 1732-1166 - Language:
- English
- Publication year:
- 2007
- Bibliographic description:
- Wójcikowski M., Pankiewicz B.: COMPARISON OF SOFTWARE AND HARDWARE REALIZATION OF AES CRYPTOGRAPHIC ALGORITHM// Zeszyty Naukowe Wydziału ETI Politechniki Gdańskiej. Technologie Informacyjne. -Vol. 14., (2007), s.589-592
- Verified by:
- Gdańsk University of Technology
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