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Abstract
The work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is represented as the program in C++. The performed design experiments had to show whether the obtained structures of TCS/RNS converter are acceptable with respect to speed and hardware complexity. The other aim of the work was to examine whether it is enough to write the program in C++ with the use of basic arithmetic operators or bit–level description is necessary. Finally, we present the discussion of results of the TCS/RNS converter design in Xilinx Vivado HLS environment.
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- Accepted or Published Version
- DOI:
- Digital Object Identifier (open in new tab) 10.21008/j.1897-0737.2017.91.0014
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- Category:
- Articles
- Type:
- artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
- Published in:
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Poznan University of Technology Academic Journals. Electrical Engineering
pages 143 - 154,
ISSN: 1897-0737 - Language:
- English
- Publication year:
- 2017
- Bibliographic description:
- Smyk R., Czyżak M.: HIGH LEVEL SYNTHESIS IN FPGA OF TCS/RNS CONVERTER// Poznan University of Technology Academic Journals. Electrical Engineering. -., nr. 91 (2017), s.143-154
- DOI:
- Digital Object Identifier (open in new tab) 10.21008/j.1897-0737.2017.91.0014
- Verified by:
- Gdańsk University of Technology
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