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Abstract
The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA–based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.
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Authors (6)
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Grzegorz Mrugalski
- Mentor Graphics) .
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Nilanjan Mukherejee
- Mentor Graphics) .
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Artur Pogiel
- Mentor Graphics) .
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Janusz Rajski
- Mentor Graphics) .
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Jerzy Tyszer
- Poznan University .
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Keywords
Details
- Category:
- Conference activity
- Type:
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Title of issue:
- IEEE Asian Test Symposium 2014, Proceedings strony 74 - 80
- Language:
- English
- Publication year:
- 2014
- Bibliographic description:
- Mrugalski G., Mukherejee N., Pogiel A., Rajski J., Trawka M., Tyszer J.: High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs// IEEE Asian Test Symposium 2014, Proceedings/ : IEEE, 2014, s.74-80
- DOI:
- Digital Object Identifier (open in new tab) 10.1109/ats.2014.25
- Verified by:
- Gdańsk University of Technology
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