Abstract
The paper presents the results of high-level synthesis (HLS) of multi-operand adders in FPGA using the Vivado Xilinx environment. The aim was to estimate the hardware amount and latency of adders described in C-code. The main task of the presented experiments was to compare the implementations of the carry-save adder (CSA) type multi-operand adders obtained as the effect of the HLS synthesis and those based on the basic component being 4-operand adder with fast carry-chain available in FPGA’s implemented in Verilog. However, the HLS synthesis simplifies the design and prototyping process but the received results indicate that the circuit obtained as the result of such synthesis requires twice more resources and is slower than its counterpart design using Verilog.
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- Category:
- Articles
- Type:
- artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
- Published in:
-
Przegląd Elektrotechniczny
pages 170 - 173,
ISSN: 0033-2097 - Language:
- English
- Publication year:
- 2018
- Bibliographic description:
- Smyk R., Czyżak M.: Implementation of multi-operand addition in FPGA using high-level synthesis// Przegląd Elektrotechniczny. -., nr. 2 (2018), s.170-173
- DOI:
- Digital Object Identifier (open in new tab) 10.15199/48.2018.02.39
- Bibliography: test
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- Wallace C. S., A Suggestion for a Fast Multiplier, IEEE Transactions on Electronic Computers, 13 (1964), No. 1, 14-17 open in new tab
- Dadda L., Some schemes for fast serial input multipliers, Alta Frequenza, 53 (1965), No. 34, 349-356 open in new tab
- Gajski D. D., Parallel Compressors, IEEE Transactions on Computers, C-29 (1980), No. 5, 393-398 open in new tab
- Dormido S., Canto M., Synthesis of Generalized Parallel Counters, IEEE Transactions on Electronic Computers, C-30 (1981), No. 9, 699-703 open in new tab
- Altera, Stratix-IV device handbook, 2015
- Xilinx, Virtex-5 family overview lx, lxt, and sxt platforms, Xilinx Inc, San Jose, Calif, USA, 2010
- Xilinx, Virtex-6 FPGA data sheets, Xilinx Inc, San Jose, Calif, USA, 2010
- Parandeh-Afshar H., Neogy A., Brisk P., Ienne P., Compressor tree synthesis on commercial high-performance FPGAs, ACM Transactions on Reconfigurable Technology and Systems, 4 (2011), No. 4, art. no. 39 open in new tab
- Parandeh-Afshar H., Neogy A., Brisk P., Ienne P., Efficient synthesis of compressor trees on fpgas, In Proceedings of the 2008 Asia and South Pacific Design Automation Conference, ASPDAC '08, IEEE Computer Society Press, Los Alamitos, CA, USA, 2011, 138-143 open in new tab
- Parandeh-Afshar H., Neogy A., Brisk P., Ienne P., Exploiting fast carrychains of FPGAs for designing compressor trees, Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009, 242-249 open in new tab
- Parandeh-Afshar H., Neogy A., Brisk P., Ienne P., Improving synthesis of compressor trees on FPGAs via integer linear programming, Proceedings of the Design, Automation and Test Conference in Europe (DATE '08), 2008, 1256-1261 open in new tab
- Parandeh-Afshar H., Closing the gap between FPGA and ASIC: Balancing flexibility and efficiency, PhD thesis, ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE, 2012
- Kumm M., Zipf P., Efficient high speed compression trees on Xilinx FPGAs, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen(MBMV '14), 2014
- Kumm M., Zipf P., Pipelined compressor tree optimization using integer linear programming, Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014, 1-8 open in new tab
- Brunie N., de Dinechin F., Istoan M., Sergent G., Illyes K., Popa B., Arithmetic core generation using bit heaps, 3rd International Conference on Field Programmable Logic and Applications, Porto, Portugal, 2013, 1-8 open in new tab
- De Dinechin F., FloPoCo project, [web page] open in new tab
- Khurshid B., Mir R.N., High Efficiency Generalized Parallel Counters for Xilinx FPGAs, EEE 22nd International Conference on High Performance Computing (HiPC), 2015, 40-46 open in new tab
- Matsunaga T., Kimura S., Matsunaga Y., Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs, Proceedings of the 17th IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '11), 2011, 217-222 open in new tab
- Matsunaga T., Kimura S., Matsunaga Y., Multi-operand adder synthesis targeting fpgas, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 94 (2011), No. 12, 2579-2586 open in new tab
- Matsunaga T., Kimura S., Matsunaga Y., An exact approach for gpc-based compressor tree synthesis, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E96-A (2013), No. 12, 2553-2560 open in new tab
- Xilinx, Vivado design suite user guide : High-level synthesis, ug871, IXilinx Inc, San Jose, Calif, USA, 2014
- Cony J. et al., High-level synthesis for FPGAs: from prototyping to deployment, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (2011), No. 4, 473-491
- Brent, R.P., Kung, H.T., A Regular Layout for Parallel Adders, IEEE Transactions on Computers, C-31 (1982), No. 3, 260-264 open in new tab
- Sources of funding:
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- Statutory activity/subsidy
- Verified by:
- Gdańsk University of Technology
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