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Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager

Abstract

The paper presents pixel receivers for massively parallel transmission of video signal between capacitive coupled integrated circuits (ICs). The receivers meet the key requirements for massively parallel transmission, namely low-power consumption below a single μW, small area of less than 205 μm2, high sensitivity better than 160 mV, and good immunity to crosstalk. The receivers were implemented and measured in a 3-D IC (two face-to-face stacked chips fabricated in CMOS 180 nm process). The maximum throughput of 20 Mbps of single receiver has been achieved using a return-to-zero (RZ) code. The static and dynamic power consumption of the single receiver are below 0.2 μW and 0.3 μW/MHz, respectively. The design approach for cost-effective inter-chip massively parallel transmission of photosensor signals with pulse position modulation (PPM) has been also performed. With this approach and the developed receivers it is possible to transfer between chips 9-10 bit images at a speed of over 1k fps.

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Category:
Articles
Type:
artykuły w czasopismach
Published in:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS no. 67, pages 2556 - 2565,
ISSN: 1549-8328
Language:
English
Publication year:
2020
Bibliographic description:
Blakiewicz G., Kłosowski M., Jendernalik W., Jakusz J., Szczepański S.: Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager// IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS -Vol. 67,iss. 8 (2020), s.2556-2565
DOI:
Digital Object Identifier (open in new tab) 10.1109/tcsi.2020.2984454
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