Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager - Publikacja - MOST Wiedzy

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Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager

Abstrakt

The paper presents pixel receivers for massively parallel transmission of video signal between capacitive coupled integrated circuits (ICs). The receivers meet the key requirements for massively parallel transmission, namely low-power consumption below a single μW, small area of less than 205 μm2, high sensitivity better than 160 mV, and good immunity to crosstalk. The receivers were implemented and measured in a 3-D IC (two face-to-face stacked chips fabricated in CMOS 180 nm process). The maximum throughput of 20 Mbps of single receiver has been achieved using a return-to-zero (RZ) code. The static and dynamic power consumption of the single receiver are below 0.2 μW and 0.3 μW/MHz, respectively. The design approach for cost-effective inter-chip massively parallel transmission of photosensor signals with pulse position modulation (PPM) has been also performed. With this approach and the developed receivers it is possible to transfer between chips 9-10 bit images at a speed of over 1k fps.

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Accepted albo Published Version
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Copyright (2020 IEEE)

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Kategoria:
Publikacja w czasopiśmie
Typ:
artykuły w czasopismach
Opublikowano w:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS nr 67, strony 2556 - 2565,
ISSN: 1549-8328
Język:
angielski
Rok wydania:
2020
Opis bibliograficzny:
Blakiewicz G., Kłosowski M., Jendernalik W., Jakusz J., Szczepański S.: Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager// IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS -Vol. 67,iss. 8 (2020), s.2556-2565
DOI:
Cyfrowy identyfikator dokumentu elektronicznego (otwiera się w nowej karcie) 10.1109/tcsi.2020.2984454
Bibliografia: test
  1. M. Kłosowski, W. Jendernalik, J. Jakusz, G. Blakiewicz, and S. Szczepański, "A CMOS pixel with embedded ADC, digital CDS and gain correction capability for massively parallel imaging array," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 1, pp. 38-49, Jan. 2017. otwiera się w nowej karcie
  2. D. X. D. Yang, B. Fowler, and A. El Gamal, "A Nyquist-rate pixel-level ADC for CMOS image sensors," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 348-356, Mar. 1999. otwiera się w nowej karcie
  3. M. Sakakibara et al., "A 6.9-μm pixel-pitch back-illuminated global shutter CMOS image sensor with pixel-parallel 14-bit subthreshold ADC," IEEE J. Solid-State Circuits, vol. 53, no. 11, pp. 3017-3025, Nov. 2018. otwiera się w nowej karcie
  4. T. Takahashi et al., "A stacked CMOS image sensor with array- parallel ADC architecture," IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1061-1070, Apr. 2018. otwiera się w nowej karcie
  5. S. J. Carey, D. R. W. Barr, B. Wang, A. Lopich, and P. Dudek, "Live demonstration: A sensor-processor array integrated circuit for high- speed real-time machine vision," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Melbourne, VIC, Australia, Jun. 2014, p. 447. otwiera się w nowej karcie
  6. S. J. Carey, A. Lopich, D. R. W. Barr, B. Wang, and P. Dudek, "A 100,000 fps vision sensor with embedded 535 GOPS/W 256×256 SIMD processor array," in Proc. VLSI Circuits Symp., Kyoto, Japan, Jun. 2013, pp. 182-183. otwiera się w nowej karcie
  7. A. Lopich and P. Dudek, "ASPA: Focal plane digital processor array with asynchronous processing capabilities," in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, USA, May 2008, pp. 1592-1596. otwiera się w nowej karcie
  8. S. Sukegawa et al., "A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 484-485. otwiera się w nowej karcie
  9. Y. Oike et al., "8.3 M-Pixel 480-fps global-shutter CMOS image sensor with gain-adaptive column ADCs and chip-on-chip stacked integration," IEEE J. Solid-State Circuits, vol. 52, no. 4, pp. 985-993, Apr. 2017. otwiera się w nowej karcie
  10. O. Skorka and D. Joseph, "Design and fabrication of vertically-integrated CMOS image sensors," Sensors, vol. 11, no. 5, pp. 4512-4538, Apr. 2011, doi: 10.3390/s110504512. otwiera się w nowej karcie
  11. R. J. Drost, R. D. Hopkins, R. Ho, and I. E. Sutherland, "Proximity com- munication," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1529-1535, Sep. 2004. otwiera się w nowej karcie
  12. L. Luo, J. M. Wilson, S. E. Mick, J. Xu, L. Zhang, and P. D. Franzon, "3 Gb/s AC coupled chip-to-chip communication using a low swing pulse receiver," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 287-296, Jan. 2006. otwiera się w nowej karcie
  13. A. Fazzi et al., "3-D capacitive interconnections for wafer-level and die-level assembly," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2270-2282, Oct. 2007. otwiera się w nowej karcie
  14. A. Fazzi et al., "3-D capacitive interconnections with mono-and bi-directional capabilities," J. Solid-State Circuits, vol. 43, no. 1, pp. 275-284, Jan. 2008. otwiera się w nowej karcie
  15. G.-S. Kim, M. Takamiya, and T. Sakurai, "A 25-mV-sensitivity 2-Gb/s optimum-logic-threshold capacitive-coupling receiver for wire- less wafer probing systems," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 9, pp. 709-713, Sep. 2009.
  16. M.-T.-L. Aung, T. H. Lim, T. Yoshikawa, and T. T.-H. Kim, "2.31- Gb/s/ch area-efficient crosstalk canceled hybrid capacitive coupling interconnect for 3-D integration," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 8, pp. 2703-2711, Aug. 2016. otwiera się w nowej karcie
  17. W. R. Davis et al., "Demystifying 3D ICs: The pros and cons of going vertical," IEEE Design Test Comput., vol. 22, no. 6, pp. 498-510, Jun. 2005. otwiera się w nowej karcie
  18. A. Majumdar, J. E. Cunningham, and A. V. Krishnamoorthy, "Alignment and performance considerations for capacitive, inductive, and optical proximity communication," IEEE Trans. Adv. Packag., vol. 33, no. 3, pp. 690-701, Aug. 2010. otwiera się w nowej karcie
  19. W. Jendernalik, "On analog comparators for CMOS digital pixel appli- cations. A comparative study," Bull. Polish Acad. Sci. Tech. Sci., vol. 64, no. 2, pp. 271-278, Jun. 2016, doi: 10.1515/bpasts-2016-0030. otwiera się w nowej karcie
  20. W. Jendernalik, "An ultra-low-energy analog comparator for A/D con- verters in CMOS image sensors," Circuits, Syst., Signal Process., vol. 36, no. 12, pp. 4829-4843, Dec. 2017, doi: 10.1007/s00034-017- 0630-6. otwiera się w nowej karcie
  21. M. Klosowski, "A power-efficient digital technique for gain and offset correction in slope ADCs," IEEE Trans. Circuits Syst. II, Exp. Briefs, early access, Jul. 12, 2019, doi: 10.1109/TCSII.2019.2928183. otwiera się w nowej karcie
  22. M. Kłosowski, "Hybrid-mode single-slope ADC with improved lin- earity and reduced conversion time for CMOS image sensors," Int. J. Circuit Theory Appl., vol. 48, no. 1, pp. 28-41, Jan. 2020, doi: 10.1002/cta.2713. otwiera się w nowej karcie
  23. M. Nabavi, F. Ramezankhani, and M. Shams, "Optimum pMOS-to- nMOS width ratio for efficient subthreshold CMOS circuits," IEEE Trans. Electron Devices, vol. 63, no. 3, pp. 916-924, Mar. 2016. otwiera się w nowej karcie
Weryfikacja:
Politechnika Gdańska

wyświetlono 53 razy

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