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Search results for: FPGAS
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Network on Chip implementation using FPGAs resources
PublicationW artykule przedstawiono implementację sieci typu ''Network on Chip'' w układach FPGA. Sieci typu ''Network on Chip'' stały się bardzo interesującym i obiecującym rozwiązaniem dla systemów typu ''System on Chip'' które charakteryzują się intensywną komunikacją wewnętrzną. Ze względu na inne paradygmaty projektowania nie ma obecnie dostępnych efektywnych platform do budowy prototypów sieci typu ''Network on Chip'' i ich weryfikacji....
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Gradient adaptive lattice filter in FPGAS-implementation issues
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Verification and Benchmarking in MPA Coprocessor Design Process
PublicationThis paper presents verification and benchmarking required for the development of a coprocessor digital circuit for integer multiple-precision arithmetic (MPA). Its code is developed, with the use of very high speed integrated circuit hardware description language (VHDL), as an intellectual property core. Therefore, it can be used by a final user within their own computing system based on field-programmable gate arrays (FPGAs)....
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Open-Source Coprocessor for Integer Multiple Precision Arithmetic
PublicationThis paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore,...
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Routing Method for Interplanetary Satellite Communication in IoT Networks Based on IPv6
PublicationThe matter of interplanetary network (IPN) connection is a complex and sophisticated topic. Space missions are aimed inter alia at studying the outer planets of our solar system. Data transmission itself, as well as receiving data from satellites located on the borders of the solar system, was only possible thanks to the use of powerful deep space network (DSN) receivers, located in various places on the surface of the Earth. In...
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Speed sensorless induction motor drive with predictive current controller
PublicationToday, speed sensorless modes of operation are becoming standard solutions in the area of electric drives. This paper presents a speed sensorless control system of an induction motor with a predictive current controller. A closed-loop estimation system with robustness against motor parameter variation is used for the control approach. The proposed algorithm has been implemented using field-programmable gate arrays (FPGAs) and a...
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FPGA implementation of the multiplication operation in multiple-precision arithmetic
PublicationAlthough standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing systems allows one to implement...
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IP Core of Coprocessor for Multiple-Precision-Arithmetic Computations
PublicationIn this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. The developed digital...
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Implementation of Addition and Subtraction Operations in Multiple Precision Arithmetic
PublicationIn this paper, we present a digital circuit of arithmetic unit implementing addition and subtraction operations in multiple-precision arithmetic (MPA). This adder-subtractor unit is a part of MPA coprocessor supporting and offloading the central processing unit (CPU) in computations requiring precision higher than 32/64 bits. Although addition and subtraction operations of two n-digit numbers require O(n) operations, the efficient...