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Search results for: cmos imager
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Zespół Systemów Mikroelektronicznych
Research Potential* projektowania I optymalizacji układów i systemów mikroelektronicznych * zaawansowane metody projektowania i optymalizacji analogowych filtrów aktywnych * programowanie układów scalonych (FPGA, CPLD, SPLD, FPAA) * układy specjalizowane ASIC * synteza systemów o małym poborze mocy * projektowanie topografii układów i zagadnień kompatybilności elektromagnetycznej * modelowania przyrządów półprzewodnikowych * modelowania właściwości...
Other results Pokaż wszystkie wyniki (6)
Search results for: cmos imager
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Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager
PublicationThe paper presents pixel receivers for massively parallel transmission of video signal between capacitive coupled integrated circuits (ICs). The receivers meet the key requirements for massively parallel transmission, namely low-power consumption below a single μW, small area of less than 205 μm2, high sensitivity better than 160 mV, and good immunity to crosstalk. The receivers were implemented and measured in a 3-D IC (two face-to-face...
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Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
PublicationIn the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated...
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Hybrid‐mode single‐slope ADC with improved linearity and reduced conversion time for CMOS image sensors
PublicationIn the paper, a single‐slope analog‐to‐digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid‐mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single‐slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion...
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CMOS realisation of analogue processor for early vision processing
PublicationThe architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms ispresented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated usinga 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 framesper second, or achieve very low power...
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Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 µm CMOS technology
PublicationThe article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 µm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image...