FPGA realization of an improved alpha max plus beta min algorithm

Robert Smyk; Maciej Czyżak

FPGA realization of an improved alpha max plus beta min algorithm

Abstract

The generalized improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. In case of four approximation regions it is possible to reduce the peak error form 3.95% to 0.33%. This is attained by determination of the approximate ratio of arguments and adequate selection of algorithm coefficients. Four approximation regions are used and hence four sets of coefficients. Also a Xilinx FPGA implementation for 12-bit sign magnitude numbers is shown.

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Keywords

MAGNITUDE ESTIMATION, FPGA

Details

Category:: Articles
Type:: artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
Published in:: Poznan University of Technology Academic Journals. Electrical Engineering no. 80, pages 151 - 160,
ISSN: 1897-0737
Language:: English
Publication year:: 2014
Bibliographic description:: Smyk R., Czyżak M.: FPGA realization of an improved alpha max plus beta min algorithm// Poznan University of Technology Academic Journals. Electrical Engineering. -Vol. 80., (2014), s.151-160
Verified by:: Gdańsk University of Technology