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Abstract
This paper briefly introduces side channel attacks on cryptographic hardware with special emphasis on differential power analysis(DPA). Based on existing countermeasures against DPA, design method combining power equalization for synchronous and combinatorialcircuits has been proposed. AES algorithm has been implemented in Xilinx Spartan II-E field programmable gate array (FPGA) deviceusing the standard and power-equalized methods. Power traces for DPA have been collected using XPower tool. Simulation results showthat standard AES implementation can be broken after N=500 encryptions, while power-equalized counterpart shows no correlation between power consumption and the cipher key after N=2000 encryptions.
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- Category:
- Articles
- Type:
- artykuł w czasopiśmie wyróżnionym w JCR
- Published in:
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Bulletin of the Polish Academy of Sciences-Technical Sciences
no. 58,
pages 125 - 128,
ISSN: 0239-7528 - Language:
- English
- Publication year:
- 2010
- Bibliographic description:
- Strachacki M., Szczepański S.: Power equalization of AES FPGA implementation// Bulletin of the Polish Academy of Sciences-Technical Sciences. -Vol. 58, iss. Iss. 1 (2010), s.125-128
- Verified by:
- Gdańsk University of Technology
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