Search
Abstract
The paper presents application called FIReWORK, that allows for automatic creation of the VHDL hardware structures of FIR filters. Automat- ically generated specialized hardware solutions dedicated to the FPGA and ASIC are commonly known as Intellectual Property Cores. The essential fu- ture of the application is easy initialization of FIR filter parameters in GUI, and then automatically design, calculate and generate the IP Core struc- ture of the filter. The hardware realization is based on the Residue Number System, as a main arithmetic. Current structure of the application, the main objectives of the project, design assumptions and benefits are discussed. Keywords: FIR filtering, FPGA, hardware generation, IP Core, software generator, VHDL
Cite as
Full text
full text is not available in portal
Keywords
Details
- Category:
- Articles
- Type:
- artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
- Published in:
-
Journal of Applied Computer Science
no. 21,
pages 135 - 149,
ISSN: 1507-0360 - Language:
- English
- Publication year:
- 2013
- Bibliographic description:
- Smyk R.: FIReWORK: FIR Filters Hardware Structures Auto-Generator// Journal of Applied Computer Science. -Vol. 21., nr. 1 (2013), s.135-149
- Verified by:
- Gdańsk University of Technology
seen 63 times