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Modeling the effect of parasitic capacitances on the dead-time distortion in multilevel NPC inverters
Abstract
A simple model is derived and verified for evaluating the effect of parasitic capacitances on the dead-time related voltage distortion in multilevel NPC voltage source inverters. The model permits well-defined and precise compensation of dead-time distortion, exhibiting meaningful improvement on compensation methods neglecting the effects of parasitic capacitances. A simple formula is given for evaluating the capacitances as serial/parallel connections of transistor capacitances and external capacitances (introduced by the cables and load).
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Authors (4)
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Krzysztof Jakub Szwarc
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Details
- Category:
- Conference activity
- Type:
- materiały konferencyjne indeksowane w Web of Science
- Title of issue:
- 2011 IEEE International Symposium on Industrial Electronics (ISIE) strony 0 - 0
- Language:
- English
- Publication year:
- 2011
- Bibliographic description:
- Szwarc K., Cichowski A., Nieznański J., Szczepankowski P..: Modeling the effect of parasitic capacitances on the dead-time distortion in multilevel NPC inverters, W: 2011 IEEE International Symposium on Industrial Electronics (ISIE), 2011, ,.
- DOI:
- Digital Object Identifier (open in new tab) 10.1109/isie.2011.5984442
- Verified by:
- Gdańsk University of Technology
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