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Search results for: CARRY-SAVE ADDERS, GENERALIZED PARALLEL COUNTERS, MULTI-OPERAND ADDITION, FPGA
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Implementation of multi-operand addition in FPGA using high-level synthesis
PublicationThe paper presents the results of high-level synthesis (HLS) of multi-operand adders in FPGA using the Vivado Xilinx environment. The aim was to estimate the hardware amount and latency of adders described in C-code. The main task of the presented experiments was to compare the implementations of the carry-save adder (CSA) type multi-operand adders obtained as the effect of the HLS synthesis and those based on the basic component...
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Realization of multi-operand modular adders in the FPGA technology
PublicationW pracy opisano projektowanie i realizację struktur wielooperandowych sumatorów modularnych (MOMA) w środowisku Xilinx FPGA z użyciem technologii Virtex-6. Projekt oparty jest na pamięciach LUT (26x1), które symulują małe pamięci RAM służące jako podstawowy komponent do realizacji sumatorów. W pracy pokazano MOMA dla dodawania modularnego operandów 5-bitowych. Najpierw rozważono ogólne struktury MOMA i następnie dwa podstawowe...
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Design and realization of two-operand modular adders in the FPGA
PublicationW pracy zaprezentowano strukturę sumatorów modularnych w środowisku Xilinx z użyciem rodziny układów Virtex-6. Rozważono dwa typy sumatorów, jeden dla modułów 5-bitowych i drugi dla 6-bitowych. Zaprojektowano ich struktury i podano eksperymentalne wyniki implementacji.
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High-Speed Binary-to-Residue Converter Design Using 2-Bit Segmentation of the Input Word
PublicationIn this paper a new approach to the design of the high-speed binary-to-residue converter is proposed that allows the attaining of high pipelining rates by eliminating memories used in modulo m generators. The converter algorithm uses segmentation of the input binary word into 2-bit segments. The use and effects of the input word segmentation for the synthesis of converters for five-bit moduli are presented. For the number represented...
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Pipelined Two-Operand Modular Adders
PublicationPipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The structure of pipelined TOMAs is usually obtained by inserting an appropriate number of pipeline register layers within...
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Pipelined sceling of signed residue numbers with the mixed-radix conversion in the programmable gate array
PublicationIn this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System (MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue reprezentation of scaled terms, binary addition of these representations...
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Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection
PublicationA scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues...
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Digital structures for high-speed signal processing
PublicationThe work covers several issues of realization of digital structures for pipelined processing of real and complex signals with the use of binary arithmetic and residue arithmetic. Basic rules of performing operations in residue arithmetic are presented along with selected residue number systems for processing of complex signals and computation of convolution. Subsequently, methods of conversion of numbers from weighted systems to...
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Planning optimised multi-tasking operations under the capability for parallel machining
PublicationThe advent of advanced multi-tasking machines (MTMs) in the metalworking industry has provided the opportunity for more efficient parallel machining as compared to traditional sequential processing. It entailed the need for developing appropriate reasoning schemes for efficient process planning to take advantage of machining capabilities inherent in these machines. This paper addresses an adequate methodical approach for a non-linear...
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Multi-core processing system for real-time image processing in embedded computer vision applications
PublicationW artykule opisano architekturę wielordzeniowego programowalnego systemu do przetwarzania obrazów w czasie rzeczywistym. Dane obrazu są przetwarzane równocześnie przez wszystkie procesory. System umożliwia niskopoziomowe przetwarzanie obrazów,np. odejmowanie tła, wykrywanie obiektów ruchomych, transformacje geometryczne, indeksowanie wykrytych obiektów, ocena ich kształtu oraz podstawowa analiza trajektorii ruchu. Ang:This paper...
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Gasification of Densified Biomass (DB) and Municipal Solid Wastes (MSW) Using HTA/SG Technology
PublicationThe necessity of economical and rational use of natural energy sources caused a rapid development of research on the possibilities of using non‐conventional energy resources. Taking the above into account, a new technological process of thermochemical conversion of biomass and communal waste, commonly known as High Temperature Air/Steam Gasification (HTA/SG) and Multi‐Staged Enthalpy Extraction Technology (HTAG‐MEET), was developed....