Selection of circuit geometry for miniaturized microwave components based on concurrent optimization of performance and layout area - Publikacja - MOST Wiedzy

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Selection of circuit geometry for miniaturized microwave components based on concurrent optimization of performance and layout area

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The paper presents a framework for automated EM-driven circuit geometry selection of miniaturized microwave components. Selection of a particular layout is based directly on miniaturization rates achieved for a set of candidate circuit geometries. Size reduction of the considered structures is obtained by replacing their main building blocks (i.e., conventional transmission lines) with slow-wave composite cells and meander lines. The proposed method primarily aims at minimization of the structure layout area by adjusting all relevant geometry parameters of its compact building blocks. At the same time, the process ensures satisfying the assumed design requirements by means of a penalty function approach. The problem at hand is solved iteratively using a trust-region-embedded gradient search with the Jacobian matrix estimated at the level of a coarse-discretization EM model of individual circuit building blocks for improved computational efficiency. The proposed methodology is verified by two case studies involving branch-line and rat-race couplers. Each design example is considered in eight different layout versions. The miniaturization rates obtained for the considered circuit geometries range between 63.9% and 76% for the first application example, as well as 80.6% and 87.5% for the second one, respectively. Experimental data validate the reliability of the proposed approach.

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Kategoria:
Publikacja w czasopiśmie
Typ:
artykuł w czasopiśmie wyróżnionym w JCR
Opublikowano w:
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS nr 108, strony 287 - 294,
ISSN: 1434-8411
Język:
angielski
Rok wydania:
2019
Opis bibliograficzny:
Kurgan P., Kozieł S.: Selection of circuit geometry for miniaturized microwave components based on concurrent optimization of performance and layout area// AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS. -Vol. 108, (2019), s.287-294
DOI:
Cyfrowy identyfikator dokumentu elektronicznego (otwiera się w nowej karcie) 10.1016/j.aeue.2019.06.009
Weryfikacja:
Politechnika Gdańska

wyświetlono 155 razy

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