Wyszukiwarka
Abstrakt
In this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. The developed digital circuit of the coprocessor works with integer numbers of precision approaching maximally 32 kbits. Our IP core is developed using the very high speed integrated circuit hardware description language (VHDL) and simulated assuming implementation in field-programmable gate arrays (FPGAs). It exchanges data using three 64-bit data buses whereas a code for execution on the coprocessor is fetched from a dedicated 8-bit bus (all buses in AMBA standard - AXI Stream). An instruction set of the coprocessor currently consists of 7 instructions including multiplication, addition and subtraction. The computations can maximally employ 16 registers of the length 32k bits. Simulation results assuming implementation on Zynq system on chip (SoC) show that computations of the factorial (n!) for n=1000 take 326.4 μsec. Such a design currently requires 7982 look-up tables (LUTs), 10400 flip-flops (FFs), 33 block RAMs (BRAMs) and 28 DSP modules. The processor is aimed to provide scalability allowing one to use the developed IP core not only in scientific computing, but also in embedded systems employing encryption based on MPA.
Cytowania
-
3
CrossRef
-
0
Web of Science
-
3
Scopus
Autorzy (2)
-
Kamil Rudnicki dr
Cytuj jako
Pełna treść
- Wersja publikacji
- Accepted albo Published Version
- Licencja
-
otwiera się w nowej karcie
Słowa kluczowe
Informacje szczegółowe
- Kategoria:
- Aktywność konferencyjna
- Typ:
- publikacja w wydawnictwie zbiorowym recenzowanym (także w materiałach konferencyjnych)
- Tytuł wydania:
- 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) strony 416 - 419
- Język:
- angielski
- Rok wydania:
- 2018
- Opis bibliograficzny:
- Rudnicki K., Stefański T.: IP Core of Coprocessor for Multiple-Precision-Arithmetic Computations// 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)/ ed. Andrzej Napieralski Łódź: Politechnika Łódzka, 2018, s.416-419
- DOI:
- Cyfrowy identyfikator dokumentu elektronicznego (otwiera się w nowej karcie) 10.23919/mixdes.2018.8436868
- Weryfikacja:
- Politechnika Gdańska
wyświetlono 66 razy
Publikacje, które mogą cię zainteresować
Open-Source Coprocessor for Integer Multiple Precision Arithmetic
- K. Rudnicki,
- T. Stefański,
- W. Żebrowski
Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale+ MPSoC
- T. Stefański,
- K. Rudnicki,
- W. Żebrowski