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Search results for: PIPELINED FFT PROCESSOR
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On simplification of residue scaling process in pipelined Radix-4 MQRNS FFT processor
PublicationResidue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent arithmetic overflow intermediate results after each butterfly have to be...
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On configuration of residue scaling process in pipelined radix-4 MQRNS FFT processor
PublicationResidue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and outputs four complex residue numbers. In order to prevent the arithmetic overflow in the succesive stage, every number has to be scaled,...
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Measurement of magnetic signals of vehicles with denoising by matched filtering with FPGA FFT processor
PublicationW artykule przedstawiono realizację systemu do analizy i identyfikacji pojazdów oparty na pomiarze indukcji magnetycznej. Proponowany system może być zastosowany do wykrywania i identyfikacji pojadów zawierających elementy ferromagnetyczne, które zaburzają pole magnetyczne ziemi. Zaburzenie to można zmierzyć przy zastosowaniu trójosiowych magnetometrów transduktorowych, pracującyh w układzie różnicowycm. Zastosowano w systemie...
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Analysis of magnetic signals of vehicles aided by matched filtering with FPGA FFT processor
PublicationW artykule przedstawiono system analizy i identyfikacji pojazdów oparty na pomiarze indukcji magnetycznej. Do tego celu jest stosowany zestaw czujników magnatycznych pracujących bezprzewodowo, który pozwala na monitorowanie ruchu pojazdów na lotniskach, w potrach i punktach kontroli granicznej. System taki może być zastosowany do wykrywania i identyfikacji pojadów zawierających elementy ferromagnetyczne, które zaburzają pole magnetyczne...
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Inrush and short circuit current identification based on real-time spectral analysis with the use of the FPGA FFT processor
PublicationW artykule przedstawiono krótkookresową analize widmową prądu załączeniowego i prądu zwarciowego transformatora w czasie rzeczywistym z zastosowaniem procesora FFT zrealizowanego w FPGA. Otrzymane widmo ułatwia rozróżnienie rodzaju prądu, co może być zastosowanei do lepszego sterowania zabezpieczneiem różnicowo-prądowym. Określono tez teoretyczne przebiegi prądów dla przyjetego modelu transformatora. Przeprowadzono ponadto analizę...
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Digital structures for high-speed signal processing
PublicationThe work covers several issues of realization of digital structures for pipelined processing of real and complex signals with the use of binary arithmetic and residue arithmetic. Basic rules of performing operations in residue arithmetic are presented along with selected residue number systems for processing of complex signals and computation of convolution. Subsequently, methods of conversion of numbers from weighted systems to...
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Pipelined Two-Operand Modular Adders
PublicationPipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The structure of pipelined TOMAs is usually obtained by inserting an appropriate number of pipeline register layers within...
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Shared processor scheduling
PublicationWe study the shared processor scheduling problem with a single shared processor to maximize total weighted overlap, where an overlap for a job is the amount of time it is processed on its private and shared processor in parallel. A polynomial-time optimization algorithm has been given for the problem with equal weights in the literature. This paper extends that result by showing an (log)-time optimization algorithm for a class...
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Acoustic Processor of the MCM Sonar
PublicationThis paper presents the concept of an acoustic processor of the mine countermeasure sonar. Developed at the Department of Marine Electronics Systems, Gdansk University of Technology, the acoustic processor is an element of the MG-89, a modernised underwater acoustic station. The focus of the article is on the modules of the processor. They are responsible for sampling analogue signals and implementing the algorithms controlling...
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Shared multi-processor scheduling
PublicationWe study shared multi-processor scheduling problem where each job can be executed on its private processor and simultaneously on one of many processors shared by all jobs in order to reduce the job’s completion time due to processing time overlap. The total weighted overlap of all jobs is to be maximized. The problem models subcontracting scheduling in supply chains and divisible load scheduling in computing. We show that synchronized...
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Acoustic Processor of the Mine Countermeasure Sonar
PublicationThis paper presents the concept of an acoustic processor of the mine countermeasure sonar. Developed at the Department of Marine Electronics Systems, Gdansk University of Technology, the acoustic processor is an element of the MG-89, an underwater acoustic station. The focus of the article is on the modules of the processor. They are responsible for sampling analogue signals and implementing the algorithms controlling the measurement...
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Pipelined division of signed numbers with the use of residue arithmetic in FPGA
PublicationAn architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length...
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Shared processor scheduling of multiprocessor jobs
PublicationWe study a problem of shared processor scheduling of multiprocessor weighted jobs. Each job can be executed on its private processor and simultaneously on possibly many processors shared by all jobs. This simultaneous execution reduces their completion times due to the processing time overlap. Each of the m shared processors may charge a different fee but otherwise the processors are identical. The goal is to maximize the total...
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Metoda szczególnego próbkowania a FFT w pomiarach elektroenergetycznych
PublicationW referacie przedstawiono podstawowe różnice pomiędzy metodami wykorzystującymi próbkowanie równomierne, a więc DFT i FFT a metodą szczególnego próbkowania, opracowaną specjalnie do pomiarów elektroenergetycznych, które wymagają dużej dokładności amplitudowej i fazowej ale ograniczonej liczby wyznaczanych harmonicznych.
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Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
PublicationIn this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algorithm based on segmentation of the divisor into two segments...
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Prediction of Processor Utilization for Real-Time Multimedia Stream Processing Tasks
PublicationUtilization of MPUs in a computing cluster node for multimedia stream processing is considered. Non-linear increase of processor utilization is described and a related class of algorithms for multimedia real-time processing tasks is defined. For such conditions, experiments measuring the processor utilization and output data loss were proposed and their results presented. A new formula for prediction of utilization was proposed...
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Fast implementation of FDTD-compatible green's function on multicore processor
PublicationIn this letter, numerically efficient implementation of the finite-difference time domain (FDTD)-compatible Green's function on a multicore processor is presented. Recently, closed-form expression of this discrete Green's function (DGF) was derived, which simplifies its application in the FDTD simulations of radiation and scattering problems. Unfortunately, the new DGF expression involves binomial coefficients, whose computations...
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Analog CMOS processor for early vision processing with highly reduced power consumption
PublicationA new approach to an analog ultra-low power visionchip design is presented. The prototype chip performs low-levelconvolutional image processing algorithms in real time. Thecircuit is implemented in 0.35 μm CMOS technology, contains64 x 64 SIMD matrix with embedded analogue processors APE(Analogue Processing Element). The photo-sensitive-matrix is of2.2 μm x 2.2 μm size, giving the density of 877 processors permm2. The matrix dissipates...
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High-speed fpga pipelined binary-to-residue converter
Publicationw pracy przedstawiono architekturę przepływowego konwertera z systemu z uzupełnieniem do 2 z systemu binarnego. zastosowano segmentację słowa wejściowego ze wstępną inwersją dla liczb ujemnych. reszty liczb reprezentowanych przez poszczególne segmenty są obliczane poprzez odczyt z pamięci adresowanej binarną reprezentacją segmentu. otrzymane reszty sumowane są w wielooperandowym sumatorze modulo z korekcją reszty dla liczb ujemnych.pracę...
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Analiza widmowa w czasie rzeczywistym prądów udarowych transformatora z zastosowaniem procesora FFT w technologii FPGA
PublicationW artykule przedstawiono krótkookresową analizę widmową prądu załączeniowego i prądu zwarciowego transformatora w czasie rzeczywistym z zastosowaniem procesora FFT zrealizowanego w FPGA. Określono tez teoretyczne przebiegi prądów dla przyjetego modelu transformatora. Przeprowadzono ponadto analizę wymagań związanych z obliczaniem prądu w czasie rzeczywistym.