Pipelined sceling of signed residue numbers with the mixed-radix conversion in the programmable gate array - Publikacja - MOST Wiedzy

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Pipelined sceling of signed residue numbers with the mixed-radix conversion in the programmable gate array

Abstrakt

In this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System (MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue reprezentation of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign is detected on the basis of the value of the most significant coefficient of the MRS reprezentation. For negative numbers their residues are adequately corrected. The basic blocks of the scaler are realized in the form of the modified two-operand modulo adders with included additional multiply and modulo reduction operations. The pipeline realization of the scaler in the Xilinx environment is shown and analyzed with respect to hardware amount and maximum pipelining frequency. The design is based on the LUTs(2 sub 6 x 1) that simulate small RAMs serving as a main component for the look-up realization.

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Kategoria:
Publikacja w czasopiśmie
Typ:
artykuły w czasopismach recenzowanych i innych wydawnictwach ciągłych
Opublikowano w:
Poznan University of Technology Academic Journals. Electrical Engineering strony 89 - 99,
ISSN: 1897-0737
Język:
angielski
Rok wydania:
2013
Opis bibliograficzny:
Czyżak M., Smyk R., Ulman Z.: Pipelined sceling of signed residue numbers with the mixed-radix conversion in the programmable gate array// Poznan University of Technology Academic Journals. Electrical Engineering. -., nr. 76 (2013), s.89-99
Weryfikacja:
Politechnika Gdańska

wyświetlono 111 razy

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