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Search results for: CMOS IMAGE SENSOR (CIS)
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An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing
PublicationA new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3x3 kernel. The proof-of-concept circuit is implemented in 0.35 µm CMOS technology,...
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Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 µm CMOS technology
PublicationThe article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 µm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image...
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A High-Efficient Measurement System With Optimization Feature for Prototype CMOS Image Sensors
PublicationIn this paper, a gray-scale CMOS image sensor (CIS) characterization system with an optimization feature has been proposed. By using a very fast and precise control of light intensity, based on the pulsewidth-modulation method, it is avoided to measure the illuminance every time. These features accelerate the multicriteria CIS optimization requiring many thousands of measurements. The system throughput is 2.5 Gb/s, which allows...
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An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors
PublicationThis paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis...
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CMOS implementation of an analogue median filter for image processing in real time
PublicationAn analogue median filter, realised in a 0.35 μm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of...
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Marek Wójcikowski dr hab. inż.
PeopleMarek Wójcikowski graduated in 1993 from the Department of Electronics at Gdansk University of Technology (GUT). In 2002 he obtained a doctoral degree in the field of electronics and in 2016 he obtained a habilitation at the Faculty of Electronics, Telecommunications and Informatics at GUT. From the beginning of his career he is associated with GUT: first as an assistant (years 1994-2002) and then as assistant professor (since...
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Hybrid‐mode single‐slope ADC with improved linearity and reduced conversion time for CMOS image sensors
PublicationIn the paper, a single‐slope analog‐to‐digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid‐mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single‐slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion...
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Analogue CMOS ASICs in Image Processing Systems
PublicationIn this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs)...
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Light-Powered Starter for Micro-Power Boost DC–DC Converter for CMOS Image Sensors
PublicationThe design of a starter for a low-voltage, micro-power boost DC–DC converter intended for powering CMOS image sensors is presented. A unique feature of the starter is extremely low current, below 1 nA, supplying its control circuit. Therefore, a high-voltage (1.3 V) configuration of series-connected photovoltaic diodes available in a standard CMOS process or a small external LED working in photovoltaic mode can be used as an auxiliary...
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Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
PublicationIn the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated...
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an intelligent image processing sensor - the algorithm and the hardware implementation
PublicationW artykule przedstawiono algorytm przeznaczony do rozpoznawania obiektów ruchomych w obrazie do celu analizy ruchu pojazdów. Algorytm został zrealizowany w układzie FPGA.Ang.: This paper describes the idea and theimplementation of the robust algorithm dedicated toextraction of moving vehicles from real-time cameraimages for the evaluation of traffic parameters, suchas the number of vehicles, their direction of movementand their...
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Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors
PublicationThis brief presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp,...
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Analog multiplier for a low-power integrated image sensor
PublicationArtykuł przedstawia nowe podejście do projektowania tanich niskomocowych zintegrowanych sensorów optycznych. W odróżnieniu od wcześniej stosowanych rozwiązań opartych na masowym przetwarzaniu równoległym, zaproponowany mnożnik macierzowy charakteryzuje się korzystniejszymi cechami. Proponowane rozwiązanie, chociaż mniej elastyczne w sensie liczby możliwych do zaimplementowania algorytmów wstępnej obróbki obrazu, cechuje się znaczącą...
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Analog multiplier for a low-power integrated image sensor
PublicationArtykuł przedstawia nowe podejście do projektowania tanich niskomocowych zintegrowanych sensorów optycznych. W odróżnieniu od wcześniej stosowanych rozwiązań opartych na masowym przetwarzaniu równoległym, zaproponowany mnożnik macierzowy charakteryzuje się korzystniejszymi cechami. Proponowane rozwiązanie, chociaż mniej elastyczne w sensie liczby możliwych do zaimplementowania algorytmów wstępnej obróbki obrazu, cechuje się znaczącą...
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A nine-input 1.25 mW, 34 ns CMOS analog median filter for image processing in real time
PublicationIn this paper an analog voltage-mode median filter, which operates on a 3 × 3 kernel is presented. The filter is implemented in a 0.35 μm CMOS technology. The proposed solution is based on voltage comparators and a bubble sort configuration. As a result, a fast (34 ns) time response with low power consumption (1.25 mW for 3.3 V) is achieved. The key advantage of the configuration is relatively high accuracy of signal processing,...
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On analog comparators for CMOS digital pixel applications. A comparative study
PublicationVoltage comparator is the only – apart from the light-to-voltage converter – analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have...
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CNN Architectures for Human Pose Estimation from a Very Low Resolution Depth Image
PublicationThe paper is dedicated to proposing and evaluating a number of convolutional neural network architectures for calculating a multiple regression on 3D coordinates of human body joints tracked in a single low resolution depth image. The main challenge was to obtain a high precision in case of a noisy and coarse scan of the body, as observed by a depth sensor from a large distance. The regression network was expected to reason about...
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In-ADC, Rank-Order Filter for Digital Pixel Sensors
PublicationThis paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS...
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CMOS realisation of analogue processor for early vision processing
PublicationThe architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms ispresented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated usinga 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 framesper second, or achieve very low power...
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Deep neural networks for human pose estimation from a very low resolution depth image
PublicationThe work presented in the paper is dedicated to determining and evaluating the most efficient neural network architecture applied as a multiple regression network localizing human body joints in 3D space based on a single low resolution depth image. The main challenge was to deal with a noisy and coarse representation of the human body, as observed by a depth sensor from a large distance, and to achieve high localization precision....