Rok 2020

• Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager

  Publikacja

  • G. Blakiewicz
  • M. Kłosowski
  • W. Jendernalik
  • J. Jakusz
  • S. Szczepański

  - IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS - Rok 2020

  The paper presents pixel receivers for massively parallel transmission of video signal between capacitive coupled integrated circuits (ICs). The receivers meet the key requirements for massively parallel transmission, namely low-power consumption below a single μW, small area of less than 205 μm2, high sensitivity better than 160 mV, and good immunity to crosstalk. The receivers were implemented and measured in a 3-D IC (two face-to-face...

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Rok 2017

• A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array

  Publikacja

  • M. Kłosowski
  • W. Jendernalik
  • J. Jakusz
  • G. Blakiewicz
  • S. Szczepański

  - IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS - Rok 2017

  In the paper, a CMOS pixel has been proposed for imaging arrays with massively parallel image acquisition and simultaneous compensation of dark signal nonuniformity (DSNU) as well as photoresponse nonuniformity (PRNU). In our solution the pixel contains all necessary functional blocks: a photosensor and an analog-to-digital converter (ADC) with built-in correlated double sampling (CDS) integrated together. It is implemented in...

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Rok 2013

• An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

  Publikacja

  • W. Jendernalik
  • G. Blakiewicz
  • J. Jakusz
  • S. Szczepański
  • R. Piotrowski

  - IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS - Rok 2013

  A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3x3 kernel. The proof-of-concept circuit is implemented in 0.35 µm CMOS technology,...

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• Two-Rate Based Low-Complexity Variable Fractional-Delay FIR Filter Structures

  Publikacja

  • H. Johansson
  • E. Hermanowicz

  - IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS - Rok 2013

  This paper considers two-rate based structures for variable fractional-delay (VFD) finite-length impulse response (FIR) filters. They are single-rate structures but derived through a two-rate approach. The basic structure considered hitherto utilizes a regular half-band (HB) linear-phase filter and the Farrow structure with linear-phase subfilters. Especially for wide-band specifications, this structure is computationally efficient...

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Rok 2003

• Dynamic range comparison of voltage-mode and current-mode state-space Gm-Cbiquad filters in reciprocal structures

  Publikacja

  • S. Kozieł
  • S. Szczepański

  - IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS - Rok 2003

  W pracy dokonano porównania zakresu dynamicznego bikwadratowych filtrówGm-C zmiennych stanu, których struktury układowe oparte są na zasadzie tran-sformacji układu dołączonego. Przeprowadzono rozważania teoretyczne w wynikuktórych określono ogóne formuły zakresu dynamicznego dla klasy filtrów Gm-Ctrybu napięciowego i prądowego. Weryfikacja rezultatów teoretycznych byłazrealizowana za pomocą symulatora SPICE.