Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

Miron Kłosowski; Yichuang Sun

doi:10.3390/s20205921

Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

Abstrakt

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

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Autorzy (2)

Miron Kłosowski dr inż.
Yichuang Sun

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Wersja publikacji: Accepted albo Published Version
Licencja: otwiera się w nowej karcie

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Kategoria:

Publikacja w czasopiśmie

Typ:

artykuły w czasopismach

Opublikowano w:

SENSORS nr 20,
ISSN: 1424-8220

Język:

angielski

Rok wydania:

2020

Opis bibliograficzny:

Kłosowski M., Sun Y.: Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors// SENSORS -Vol. 20,iss. 20 (2020), s.5921-

DOI: