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Wyniki wyszukiwania dla: CMOS DIGITAL PIXEL
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On analog comparators for CMOS digital pixel applications. A comparative study
PublikacjaVoltage comparator is the only – apart from the light-to-voltage converter – analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have...
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A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array
PublikacjaIn the paper, a CMOS pixel has been proposed for imaging arrays with massively parallel image acquisition and simultaneous compensation of dark signal nonuniformity (DSNU) as well as photoresponse nonuniformity (PRNU). In our solution the pixel contains all necessary functional blocks: a photosensor and an analog-to-digital converter (ADC) with built-in correlated double sampling (CDS) integrated together. It is implemented in...
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In-ADC, Rank-Order Filter for Digital Pixel Sensors
PublikacjaThis paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS...
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An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing
PublikacjaA new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3x3 kernel. The proof-of-concept circuit is implemented in 0.35 µm CMOS technology,...
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Hybrid‐mode single‐slope ADC with improved linearity and reduced conversion time for CMOS image sensors
PublikacjaIn the paper, a single‐slope analog‐to‐digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid‐mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single‐slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion...
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Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors
PublikacjaIn the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated...
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Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors
PublikacjaThis brief presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp,...
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Bogdan Pankiewicz dr hab. inż.
OsobyBogdan Pankiewicz ukończył w 1993 r. Wydział Elektroniki Politechniki Gdańskiej, specjalność układy elektroniczne a w 2002 r. uzyskał stopień doktora w dziedzinie elektroniki na Wydziale ETI, PG. Od początku kariery jest związany z Politechniką Gdańską: najpierw jako asystent (lata 1994–2002), a następnie jako adiunkt (od 2002 r.) na Wydziale Elektroniki, Telekomunikacji i Informatyki. Zajmuje się projektowaniem analogowych i cyfrowych...
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An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors
PublikacjaThis paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis...
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A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs
PublikacjaIn this brief, a power-efficient digital technique for gain and offset correction in slope analog-to-digital converters (ADCs) has been proposed. The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by...