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Wyniki wyszukiwania dla: FIELD PROGRAMMABLE GATE ARRAYS, HIGH LEVEL SYNTHESIS, SYSTEMS SIMULATION
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FPGA Based Real Time Simulations of the Face Milling Process
PublikacjaThe article presents a successful implementation of the milling process simulation at the Field-Programmable Gate Array (FPGA). By using FPGA, very rigorous Real-Time (RT) simulation requirements can be met. The response time of the FPGA simulations is significantly reduced, and the time synchronization is better than in a typical RT system implemented in software. The FPGA-based approach is characterized by enormous flexibility...
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Routing Method for Interplanetary Satellite Communication in IoT Networks Based on IPv6
PublikacjaThe matter of interplanetary network (IPN) connection is a complex and sophisticated topic. Space missions are aimed inter alia at studying the outer planets of our solar system. Data transmission itself, as well as receiving data from satellites located on the borders of the solar system, was only possible thanks to the use of powerful deep space network (DSN) receivers, located in various places on the surface of the Earth. In...
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IP Core of Coprocessor for Multiple-Precision-Arithmetic Computations
PublikacjaIn this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. The developed digital...
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A New, Reconfigurable Circuit Offering Functionality of AND and OR Logic Gates for Use in Algorithms Implemented in Hardware
PublikacjaThe paper presents a programmable (using a 1-bit signal) digital gate that can operate in one of two OR or AND modes. A circuit of this type can also be implemented using conventional logic gates. However, in the case of the proposed circuit, compared to conventional solutions, the advantage is a much smaller number of transistors necessary for its implementation. Circuit is also much faster than its conventional counterpart. The...
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FPGA implementation of the multiplication operation in multiple-precision arithmetic
PublikacjaAlthough standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing systems allows one to implement...
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Verification and Benchmarking in MPA Coprocessor Design Process
PublikacjaThis paper presents verification and benchmarking required for the development of a coprocessor digital circuit for integer multiple-precision arithmetic (MPA). Its code is developed, with the use of very high speed integrated circuit hardware description language (VHDL), as an intellectual property core. Therefore, it can be used by a final user within their own computing system based on field-programmable gate arrays (FPGAs)....
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Speed sensorless induction motor drive with predictive current controller
PublikacjaToday, speed sensorless modes of operation are becoming standard solutions in the area of electric drives. This paper presents a speed sensorless control system of an induction motor with a predictive current controller. A closed-loop estimation system with robustness against motor parameter variation is used for the control approach. The proposed algorithm has been implemented using field-programmable gate arrays (FPGAs) and a...
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Power equalization of AES FPGA implementation
PublikacjaThis paper briefly introduces side channel attacks on cryptographic hardware with special emphasis on differential power analysis(DPA). Based on existing countermeasures against DPA, design method combining power equalization for synchronous and combinatorialcircuits has been proposed. AES algorithm has been implemented in Xilinx Spartan II-E field programmable gate array (FPGA) deviceusing the standard and power-equalized methods....
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Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale+ MPSoC
PublikacjaRecently, we have opened the source code of coprocessor for multiple-precision arithmetic (MPA). In this contribution, the implementation and benchmarking results for this MPA coprocessor are presented on modern Zynq Ultrascale+ multiprocessor system on chip, which combines field-programmable gate array with quad-core ARM Cortex-A53 64-bit central processing unit (CPU). In our benchmark, a single coprocessor can be up to 4.5 times...
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COMPARISON OF SYSTEM ON CHIP TECHNOLOGIES FOR SPACE APPLICATIONS
PublikacjaThe paper presents a review of technologies available for the implementation of digital and mixed signal systems, particularly the system on a chip (SoC) for space applications. The phenomena encountered in the space environment are briefly presented, together with the known solutions, regarding the design of complex electronic systems. The most important norms regarding single die integrated circuits designed for space are also...
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Open-Source Coprocessor for Integer Multiple Precision Arithmetic
PublikacjaThis paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore,...
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FPGA realization of an improved alpha max plus beta min algorithm
PublikacjaThe generalized improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. In case of four approximation regions it is possible to reduce the peak error form 3.95% to 0.33%. This...
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Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors
PublikacjaIn this paper a programmable input mode instrumentation amplifier (IA) utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field...
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Acceleration of Electromagnetic Simulations on Reconfigurable FPGA Card
PublikacjaIn this contribution, the hardware acceleration of electromagnetic simulations on the reconfigurable field-programmable-gate-array (FPGA) card is presented. In the developed implementation of scientific computations, the matrix-assembly phase of the method of moments (MoM) is accelerated on the Xilinx Alveo U200 card. The computational method involves discretization of the frequency-domain mixed potential integral equation using...
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FPGA-Based Implementation of Real Time Optical Flow Algorithm and Its Applications for Digital Image Stabilization
PublikacjaAn efficient simplification procedure of the optical flow (OF) algorithm as well as its hardware implementation using the field programmable gate array (FPGA) technology is presented. The modified algorithm is based on block matching of subsets of successive frames, and exploits one-dimensional representation of subsets as well as the adaptive adjustments of their sizes. Also, an l1-norm-based correlation function requiring no...
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FPGA-Based System for Electromagnetic Interference Evaluation in Random Modulated DC/DC Converters
PublikacjaField-Programmable Gate Array (FPGA) provides the possibility to design new “electromagnetic compatibility (EMC) friendly” control techniques for power electronic converters. Such control techniques use pseudo-random modulators (RanM) to control the converter switches. However, some issues connected with the FPGA-based design of RanM, such as matching the range of fixed-point numbers, might be challenging. The modern programming...
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FPGA Acceleration of Matrix-Assembly Phase of RWG-Based MoM
PublikacjaIn this letter, the field-programmable-gate-array accelerated implementation of matrix-assembly phase of the method of moments (MoM) is presented. The solution is based on a discretization of the frequency-domain mixed potential integral equation using the Rao-Wilton-Glisson basis functions and their extension to wire-to-surface junctions. To take advantage of the given hardware resources (i.e., Xilinx Alveo U200 accelerator card),...
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HILS for the Design of Three-Wheeled Mobile Platform Motion Surveillance System with a Use of Energy Performance Index
PublikacjaCurrent tendency in mechatronic design requires the use of comprehensive development of an environment, which gives the possibility to prototype, design, simulate and integrate with dedicated hardware. The paper discusses the Hardware-In-the-Loop Simulations (HILS) mechatronic technique, used during the design of the surveillance system based on energy performance index. The presented test configuration (physical controller – emulated...
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PROJEKTOWANIE WIELOWYMIAROWEGO REGULATORA BACKSTEPPING W UKŁADZIE DYNAMICZNEGO POZYCJONOWANIA STATKU
PublikacjaW komercyjnych systemach dynamicznego pozycjonowania statku, pomimo znacznego wzrostu poziomu automatyzacji, wykorzystywane jest nadal sterowanie typu PID. Poprawę jakości procesu pozycjonowania może umożliwić wykorzystanie bardziej efektywnych algorytmów, oferujących zaawansowane nieliniowe techniki sterowania. W artykule przedstawiono zagadnienie projektowania regulatora pozycji i kursu dla układu dynamicznego pozycjonowania...
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A new concept of PWM duty cycle computation using the Barycentric Coordinates in a Three-Dimensional voltage vectors arrangement
PublikacjaThe paper presents a novel approach to the Pulse Width Modulation (PWM) duty cycle computing for complex or irregular voltage vector arrangements in the two (2D) and three–dimensional (3D) Cartesian coordinate systems. The given vectors arrangement can be built using at least three vectors or collections with variable number of involved vectors (i.e. virtual vectors). Graphically, these vectors form a convex figure, in particular,...