Search results for: analog processor array
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Analog filter design system for field programmable analog array.
PublicationObiektowy system do automatycznego projektowania filtrów kaskadowych i symetrycznych filtrów FLF z wykorzystaniem wzmacniaczy transkonuktancyjnych OTACi bloków bikwadratowych z optymalizacją zakresu dynamiki, zniekształceń i wrażliwości. System umożliwia realizację standardowych aproksymacji charakterystyk amplitudowych oraz dowolnie zdefiniowanych przez użytkownika.
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Analog CMOS processor for early vision processing with highly reduced power consumption
PublicationA new approach to an analog ultra-low power visionchip design is presented. The prototype chip performs low-levelconvolutional image processing algorithms in real time. Thecircuit is implemented in 0.35 μm CMOS technology, contains64 x 64 SIMD matrix with embedded analogue processors APE(Analogue Processing Element). The photo-sensitive-matrix is of2.2 μm x 2.2 μm size, giving the density of 877 processors permm2. The matrix dissipates...
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A field programmable analog array for CMOS continuous-time OTA-C filter applications
PublicationW artykule opisano programowalny wzmacniacz transkonduktancyjny oraz konfigurowalny blok analogowy CAB składający się ze wzmacniacza transkonduktancyjnego, kluczy oraz programowalnego kondensatora. Z bloków CAB można zbudować uniwersalne, programowalne filtry. Wzmacniacz transkondukancyjny został przesymulowany oraz wykonany w technologii CMOS. Wyniki pomiarów pokazują, że transkonduktancja wzmacniacza może być przestrajana ponad...
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In-ADC, Rank-Order Filter for Digital Pixel Sensors
PublicationThis paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS...
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A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array
PublicationIn the paper, a CMOS pixel has been proposed for imaging arrays with massively parallel image acquisition and simultaneous compensation of dark signal nonuniformity (DSNU) as well as photoresponse nonuniformity (PRNU). In our solution the pixel contains all necessary functional blocks: a photosensor and an analog-to-digital converter (ADC) with built-in correlated double sampling (CDS) integrated together. It is implemented in...
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Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors
PublicationThis brief presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp,...
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Acoustic emission studies of the 7075 aluminium alloy pitting corrosion process
Open Research DataThe dataset contains the cyclic polarization studies and corresponding acoustic emission measurements, revealing the pitting corrosion process of the passive layer at the surface of the 7075 aluminum alloy in the borate buffer with different chloride ions concentrations, in the range between 0.05 and 25 mM.
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REALIZACJA ELEMENTÓW SKŁADOWYCH ŁĄCZA RADIOWEGO Z UŻYCIEM URZĄDZEŃ RADIA PROGRAMOWALNEGO TYPU USRP
PublicationPrzez ostatnią dekadę projektowanie systemów radiowych zaczęło w coraz większym stopniu polegać na cyfrowym przetwarzaniu sygnałów. Możliwość i moc obliczeniowa procesorów ogólnego przeznaczenia GPP (General Purpose Processor), procesorów sygnałowych DSP (Digital Signal Processor) oraz układów programowalnych FPGA (Field Programmable Gate Array) znacząco wzrosła zgodnie z prawem Moor’a. Naturalnym następstwem tego trendu było większe...
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Contactless hearing aid designed for infants
PublicationIt is a well known fact that language development through home intervention for a hearing-impaired infant should start in the early months of a newborn baby's life. The aim of this paper is to present a concept of a contactless digital hearing aid designed especially for infants. In contrast to all typical wearable hearing aid solutions (ITC, ITE, BTE), the proposed device is mounted in the infant's bed with any parts of its set-up...
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HILS for the Design of Three-Wheeled Mobile Platform Motion Surveillance System with a Use of Energy Performance Index
PublicationCurrent tendency in mechatronic design requires the use of comprehensive development of an environment, which gives the possibility to prototype, design, simulate and integrate with dedicated hardware. The paper discusses the Hardware-In-the-Loop Simulations (HILS) mechatronic technique, used during the design of the surveillance system based on energy performance index. The presented test configuration (physical controller – emulated...
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CMOS realisation of analogue processor for early vision processing
PublicationThe architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms ispresented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated usinga 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 framesper second, or achieve very low power...
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Shared processor scheduling
PublicationWe study the shared processor scheduling problem with a single shared processor to maximize total weighted overlap, where an overlap for a job is the amount of time it is processed on its private and shared processor in parallel. A polynomial-time optimization algorithm has been given for the problem with equal weights in the literature. This paper extends that result by showing an (log)-time optimization algorithm for a class...
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Acoustic Processor of the MCM Sonar
PublicationThis paper presents the concept of an acoustic processor of the mine countermeasure sonar. Developed at the Department of Marine Electronics Systems, Gdansk University of Technology, the acoustic processor is an element of the MG-89, a modernised underwater acoustic station. The focus of the article is on the modules of the processor. They are responsible for sampling analogue signals and implementing the algorithms controlling...
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A new concept of PWM duty cycle computation using the Barycentric Coordinates in a Three-Dimensional voltage vectors arrangement
PublicationThe paper presents a novel approach to the Pulse Width Modulation (PWM) duty cycle computing for complex or irregular voltage vector arrangements in the two (2D) and three–dimensional (3D) Cartesian coordinate systems. The given vectors arrangement can be built using at least three vectors or collections with variable number of involved vectors (i.e. virtual vectors). Graphically, these vectors form a convex figure, in particular,...
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Shared multi-processor scheduling
PublicationWe study shared multi-processor scheduling problem where each job can be executed on its private processor and simultaneously on one of many processors shared by all jobs in order to reduce the job’s completion time due to processing time overlap. The total weighted overlap of all jobs is to be maximized. The problem models subcontracting scheduling in supply chains and divisible load scheduling in computing. We show that synchronized...
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An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing
PublicationA new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3x3 kernel. The proof-of-concept circuit is implemented in 0.35 µm CMOS technology,...
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Acoustic Processor of the Mine Countermeasure Sonar
PublicationThis paper presents the concept of an acoustic processor of the mine countermeasure sonar. Developed at the Department of Marine Electronics Systems, Gdansk University of Technology, the acoustic processor is an element of the MG-89, an underwater acoustic station. The focus of the article is on the modules of the processor. They are responsible for sampling analogue signals and implementing the algorithms controlling the measurement...
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Shared processor scheduling of multiprocessor jobs
PublicationWe study a problem of shared processor scheduling of multiprocessor weighted jobs. Each job can be executed on its private processor and simultaneously on possibly many processors shared by all jobs. This simultaneous execution reduces their completion times due to the processing time overlap. Each of the m shared processors may charge a different fee but otherwise the processors are identical. The goal is to maximize the total...
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Multifrequency Wideband Sonar Array
PublicationThis paper describes of new approach to Multifrequency Wideband Arrays (MWA),applied piezocomposite technologies of the array elements. MWA operating in transmitting(Tx) and receiving (Rx) mode on two or three bands, requires state-of-the-art technology andefficient array designing than conventional array in which separate arrays for every band oreven separate Tx and Rx transducers/arrays are used. The new piezocomposite elements...