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Search results for: MULTI-CORE CPU
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Parallelization of Selected Algorithms on Multi-core CPUs, a Cluster and in a Hybrid CPU+Xeon Phi Environment
PublicationIn the paper we present parallel implementations as well as execution times and speed-ups of three different algorithms run in various environments such as on a workstation with multi-core CPUs and a cluster. The parallel codes, implementing the master-slave model in C+MPI, differ in computation to communication ratios. The considered problems include: a genetic algorithm with various ratios of master processing time to communication...
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Multi Queue Approach for Network Services Implemented for Multi Core CPUs
PublicationMultiple core processors have already became the dominant design for general purpose CPUs. Incarnations of this technology are present in solutions dedicated to such areas like computer graphics, signal processing and also computer networking. Since the key functionality of network core components is fast package servicing, multicore technology, due to multi tasking ability, seems useful to support packet processing. Dedicated...
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Performance assessment of OpenMP constructs and benchmarks using modern compilers and multi-core CPUs
PublicationConsidering ongoing developments of both modern CPUs, especially in the context of increasing numbers of cores, cache memory and architectures as well as compilers there is a constant need for benchmarking representative and frequently run workloads. The key metric is speed-up as the computational power of modern CPUs stems mainly from using multiple cores. In this paper, we show and discuss results from running codes such as:...
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Multi-core and Multiprocessor Implementation of Numerical Integration in Finite Element Method
PublicationThe paper presents techniques for accelerating a numerical integration process which appears in the Finite Element Method. The acceleration is achieved by taking advantages of multi-core and multiprocessor devices. It is shown that using multi-core implementation with OpenMP and a GPU acceleration using CUDA architecture allows one to achieve the speedups by a factor of 5 and 10 on a CPU and GPUs, respectively.
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Benchmarking Deep Neural Network Training Using Multi- and Many-Core Processors
PublicationIn the paper we provide thorough benchmarking of deep neural network (DNN) training on modern multi- and many-core Intel processors in order to assess performance differences for various deep learning as well as parallel computing parameters. We present performance of DNN training for Alexnet, Googlenet, Googlenet_v2 as well as Resnet_50 for various engines used by the deep learning framework, for various batch sizes. Furthermore,...
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Modified Preisach model of hysteresis in multi air gap ferrite core medium frequency transformer
PublicationThis article presents the modified Preisach model of hysteresis for a 3-phase medium frequency transformer in a 100 kW dual active bridge converter. The transformer magnetic core is assembled out of ferrite I-cores, which results in multiple parasitic air gaps. For this transformer, the hysteresis loops were measured and parameters of the Preisach model were determined. The Preisach distribution function is approximated with a...
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Multi-core processing system for real-time image processing in embedded computer vision applications
PublicationW artykule opisano architekturę wielordzeniowego programowalnego systemu do przetwarzania obrazów w czasie rzeczywistym. Dane obrazu są przetwarzane równocześnie przez wszystkie procesory. System umożliwia niskopoziomowe przetwarzanie obrazów,np. odejmowanie tła, wykrywanie obiektów ruchomych, transformacje geometryczne, indeksowanie wykrytych obiektów, ocena ich kształtu oraz podstawowa analiza trajektorii ruchu. Ang:This paper...
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Analyzing energy/performance trade-offs with power capping for parallel applications on modern multi and many core processors
PublicationIn the paper we present extensive results from analyzing energy/performance trade-offs with power capping observed on four different modern CPUs, for three different parallel applications such as 2D heat distribution, numerical integration and Fast Fourier Transform. The CPU tested represent both multi-core type CPUs such as Intel⃝R Xeon⃝R E5, desktop and mobile i7 as well as many-core Intel⃝R Xeon PhiTM x200 but also server, desktop...
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Multi-functional monodispersed SiO2-TiO2 core-shell nanostructure and TEOS in the consolidation of archaeological lime mortars surfaces
PublicationArchaeological traditional lime mortars are susceptible to many environmental conditions such as the impact of water (rain, humidity, groundwater, etc.), variation of temperatures' degrees, wind and/or pollution. Accordingly, this research aims to provide newly assessed multifunctional Nano-coating for the purpose of archaeological lime mortar protection. For this, the study combined physicochemical and mechanical characterizations...
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Effective Permeability of Multi Air Gap Ferrite Core 3-Phase Medium Frequency Transformer in Isolated DC-DC Converters
PublicationThe magnetizing inductance of the medium frequency transformer (MFT) impacts the performance of the isolated dc-dc power converters. The ferrite material is considered for high power transformers but it requires an assembly of type “I” cores resulting in a multi air gap structure of the magnetic core. The authors claim that the multiple air gaps are randomly distributed and that the average air gap length is unpredictable at the...
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Sylwester Kaczmarek dr hab. inż.
PeopleSylwester Kaczmarek received his M.Sc in electronics engineering, Ph.D. and D.Sc. in switching and teletraffic science from the Gdansk University of Technology, Gdansk, Poland, in 1972, 1981 and 1994, respectively. His research interests include: IP QoS and GMPLS and SDN networks, switching, QoS routing, teletraffic, multimedia services and quality of services. Currently, his research is focused on developing and applicability...
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Finite element matrix generation on a GPU
PublicationThis paper presents an efficient technique for fast generation of sparse systems of linear equations arising in computational electromagnetics in a finite element method using higher order elements. The proposed approach employs a graphics processing unit (GPU) for both numerical integration and matrix assembly. The performance results obtained on a test platform consisting of a Fermi GPU (1x Tesla C2075) and a CPU (2x twelve-core...
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DEPO: A dynamic energy‐performance optimizer tool for automatic power capping for energy efficient high‐performance computing
PublicationIn the article we propose an automatic power capping software tool DEPO that allows one to perform runtime optimization of performance and energy related metrics. For an assumed application model with an initialization phase followed by a running phase with uniform compute and memory intensity, the tool performs automatic tuning engaging one of the two exploration algorithms—linear search (LS) and golden section search (GSS), finds...
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Tuning a Hybrid GPU-CPU V-Cycle Multilevel Preconditioner for Solving Large Real and Complex Systems of FEM Equations
PublicationThis letter presents techniques for tuning an accelerated preconditioned conjugate gradient solver with a multilevel preconditioner. The solver is optimized for a fast solution of sparse systems of equations arising in computational electromagnetics in a finite element method using higher-order elements. The goal of the tuning is to increase the throughput while at the same time reducing the memory requirements in order to allow...
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Assessment of OpenMP Master–Slave Implementations for Selected Irregular Parallel Applications
PublicationThe paper investigates various implementations of a master–slave paradigm using the popular OpenMP API and relative performance of the former using modern multi-core workstation CPUs. It is assumed that a master partitions available input into a batch of predefined number of data chunks which are then processed in parallel by a set of slaves and the procedure is repeated until all input data has been processed. The paper experimentally...
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Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale+ MPSoC
PublicationRecently, we have opened the source code of coprocessor for multiple-precision arithmetic (MPA). In this contribution, the implementation and benchmarking results for this MPA coprocessor are presented on modern Zynq Ultrascale+ multiprocessor system on chip, which combines field-programmable gate array with quad-core ARM Cortex-A53 64-bit central processing unit (CPU). In our benchmark, a single coprocessor can be up to 4.5 times...
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IP Core of Coprocessor for Multiple-Precision-Arithmetic Computations
PublicationIn this paper, we present an IP core of coprocessor supporting computations requiring integer multiple-precision arithmetic (MPA). Whilst standard 32/64-bit arithmetic is sufficient to solve many computing problems, there are still applications that require higher numerical precision. Hence, the purpose of the developed coprocessor is to support and offload central processing unit (CPU) in such computations. The developed digital...
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Generation of large finite-element matrices on multiple graphics processors
PublicationThis paper presents techniques for generating very large finite-element matrices on a multicore workstation equipped with several graphics processing units (GPUs). To overcome the low memory size limitation of the GPUs, and at the same time to accelerate the generation process, we propose to generate the large sparse linear systems arising in finite-element analysis in an iterative manner on several GPUs and to use the graphics...
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Open-Source Coprocessor for Integer Multiple Precision Arithmetic
PublicationThis paper presents an open-source digital circuit of the coprocessor for an integer multiple-precision arithmetic (MPA). The purpose of this coprocessor is to support a central processing unit (CPU) by offloading computations requiring integer precision higher than 32/64 bits. The coprocessor is developed using the very high speed integrated circuit hardware description language (VHDL) as an intellectual property (IP) core. Therefore,...
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FPGA Acceleration of Matrix-Assembly Phase of RWG-Based MoM
PublicationIn this letter, the field-programmable-gate-array accelerated implementation of matrix-assembly phase of the method of moments (MoM) is presented. The solution is based on a discretization of the frequency-domain mixed potential integral equation using the Rao-Wilton-Glisson basis functions and their extension to wire-to-surface junctions. To take advantage of the given hardware resources (i.e., Xilinx Alveo U200 accelerator card),...