Search
Search results for: INTEL XEON INTEL XEON PHI 1
-
Benchmarking Parallel Chess Search in Stockfish on Intel Xeon and Intel Xeon Phi Processors
PublicationThe paper presents results from benchmarking the parallel multithreaded Stockfish chess engine on selected multi- and many-core processors. It is shown how the strength of play for an n-thread version compares to 1-thread version on both Intel Xeon and latest Intel Xeon Phi x200 processors. Results such as the number of wins, losses and draws are presented and how these change for growing numbers of threads. Impact of using particular...
-
Modern Platform for Parallel Algorithms Testing: Java on Intel Xeon Phi
PublicationParallel algorithms are popular method of increasing system performance. Apart from showing their properties using asymptotic analysis, proof-of-concept implementation and practical experiments are often required. In order to speed up the development and provide simple and easily accessible testing environment that enables execution of reliable experiments, the paper proposes a platform with multi-core computational accelerator:...
-
Benchmarking Performance of a Hybrid Intel Xeon/Xeon Phi System for Parallel Computation of Similarity Measures Between Large Vectors
PublicationThe paper deals with parallelization of computing similarity measures between large vectors. Such computations are important components within many applications and consequently are of high importance. Rather than focusing on optimization of the algorithm itself, assuming specific measures, the paper assumes a general scheme for finding similarity measures for all pairs of vectors and investigates optimizations for scalability...
-
Extended investigation of performance-energy trade-offs under power capping in HPC environments
Publication—In the paper we present investigation of performance-energy trade-offs under power capping using modern processors. The results are presented for systems targeted at both server and client markets and were collected from Intel Xeon E5 and Intel Xeon Phi server processors as well as from desktop and mobile Intel Core i7 processors. The results, when using power capping, show that we can find various interesting combinations of...
-
Performance assessment of OpenMP constructs and benchmarks using modern compilers and multi-core CPUs
PublicationConsidering ongoing developments of both modern CPUs, especially in the context of increasing numbers of cores, cache memory and architectures as well as compilers there is a constant need for benchmarking representative and frequently run workloads. The key metric is speed-up as the computational power of modern CPUs stems mainly from using multiple cores. In this paper, we show and discuss results from running codes such as:...
-
GPU-Accelerated LOBPCG Method with Inexact Null-Space Filtering for Solving Generalized Eigenvalue Problems in Computational Electromagnetics Analysis with Higher-Order FEM
PublicationThis paper presents a GPU-accelerated implementation of the Locally Optimal Block Preconditioned Conjugate Gradient (LOBPCG) method with an inexact nullspace filtering approach to find eigenvalues in electromagnetics analysis with higherorder FEM. The performance of the proposed approach is verified using the Kepler (Tesla K40c) graphics accelerator, and is compared to the performance of the implementation based on functions from...
-
Parallelization of large vector similarity computations in a hybrid CPU+GPU environment
PublicationThe paper presents design, implementation and tuning of a hybrid parallel OpenMP+CUDA code for computation of similarity between pairs of a large number of multidimensional vectors. The problem has a wide range of applications, and consequently its optimization is of high importance, especially on currently widespread hybrid CPU+GPU systems targeted in the paper. The following are presented and tested for computation of all vector...
-
Parallel Programming for Modern High Performance Computing Systems
PublicationIn view of the growing presence and popularity of multicore and manycore processors, accelerators, and coprocessors, as well as clusters using such computing devices, the development of efficient parallel applications has become a key challenge to be able to exploit the performance of such systems. This book covers the scope of parallel programming for modern high performance computing systems. It first discusses selected and...
-
Efficient parallel implementation of crowd simulation using a hybrid CPU+GPU high performance computing system
PublicationIn the paper we present a modern efficient parallel OpenMP+CUDA implementation of crowd simulation for hybrid CPU+GPU systems and demonstrate its higher performance over CPU-only and GPU-only implementations for several problem sizes including 10 000, 50 000, 100 000, 500 000 and 1 000 000 agents. We show how performance varies for various tile sizes and what CPU–GPU load balancing settings shall be preferred for various domain...
-
Assessment of OpenMP Master–Slave Implementations for Selected Irregular Parallel Applications
PublicationThe paper investigates various implementations of a master–slave paradigm using the popular OpenMP API and relative performance of the former using modern multi-core workstation CPUs. It is assumed that a master partitions available input into a batch of predefined number of data chunks which are then processed in parallel by a set of slaves and the procedure is repeated until all input data has been processed. The paper experimentally...
-
Single and Dual-GPU Generalized Sparse Eigenvalue Solvers for Finding a Few Low-Order Resonances of a Microwave Cavity Using the Finite-Element Method
PublicationThis paper presents two fast generalized eigenvalue solvers for sparse symmetric matrices that arise when electromagnetic cavity resonances are investigated using the higher-order finite element method (FEM). To find a few loworder resonances, the locally optimal block preconditioned conjugate gradient (LOBPCG) algorithm with null-space deflation is applied. The computations are expedited by using one or two graphical processing...
-
GPU-Accelerated Finite-Element Matrix Generation for Lossless, Lossy, and Tensor Media [EM Programmer's Notebook]
PublicationThis paper presents an optimization approach for limiting memory requirements and enhancing the performance of GPU-accelerated finite-element matrix generation applied in the implementation of the higher-order finite-element method (FEM). It emphasizes the details of the implementation of the matrix-generation algorithm for the simulation of electromagnetic wave propagation in lossless, lossy, and tensor media. Moreover, the impact...
-
DEPO: A dynamic energy‐performance optimizer tool for automatic power capping for energy efficient high‐performance computing
PublicationIn the article we propose an automatic power capping software tool DEPO that allows one to perform runtime optimization of performance and energy related metrics. For an assumed application model with an initialization phase followed by a running phase with uniform compute and memory intensity, the tool performs automatic tuning engaging one of the two exploration algorithms—linear search (LS) and golden section search (GSS), finds...
-
Block Conjugate Gradient Method with Multilevel Preconditioning and GPU Acceleration for FEM Problems in Electromagnetics
PublicationIn this paper a GPU-accelerated block conjugate gradient solver with multilevel preconditioning is presented for solving large system of sparse equations with multiple right hand-sides (RHSs) which arise in the finite-element analysis of electromagnetic problems. We demonstrate that blocking reduces the time to solution significantly and allows for better utilization of the computing power of GPUs, especially when the system matrix...
-
A memory efficient and fast sparse matrix vector product on a Gpu
PublicationThis paper proposes a new sparse matrix storage format which allows an efficient implementation of a sparse matrix vector product on a Fermi Graphics Processing Unit (GPU). Unlike previous formats it has both low memory footprint and good throughput. The new format, which we call Sliced ELLR-T has been designed specifically for accelerating the iterative solution of a large sparse and complex-valued system of linear equations arising...
-
Generation of large finite-element matrices on multiple graphics processors
PublicationThis paper presents techniques for generating very large finite-element matrices on a multicore workstation equipped with several graphics processing units (GPUs). To overcome the low memory size limitation of the GPUs, and at the same time to accelerate the generation process, we propose to generate the large sparse linear systems arising in finite-element analysis in an iterative manner on several GPUs and to use the graphics...
-
Optimization of Data Assignment for Parallel Processing in a Hybrid Heterogeneous Environment Using Integer Linear Programming
PublicationIn the paper we investigate a practical approach to application of integer linear programming for optimization of data assignment to compute units in a multi-level heterogeneous environment with various compute devices, including CPUs, GPUs and Intel Xeon Phis. The model considers an application that processes a large number of data chunks in parallel on various compute units and takes into account computations, communication including...
-
A GPU Solver for Sparse Generalized Eigenvalue Problems with Symmetric Complex-Valued Matrices Obtained Using Higher-Order FEM
PublicationThe paper discusses a fast implementation of the stabilized locally optimal block preconditioned conjugate gradient (sLOBPCG) method, using a hierarchical multilevel preconditioner to solve nonHermitian sparse generalized eigenvalue problems with large symmetric complex-valued matrices obtained using the higher-order finite-element method (FEM), applied to the analysis of a microwave resonator. The resonant frequencies of the low-order...
-
Parallelization of Selected Algorithms on Multi-core CPUs, a Cluster and in a Hybrid CPU+Xeon Phi Environment
PublicationIn the paper we present parallel implementations as well as execution times and speed-ups of three different algorithms run in various environments such as on a workstation with multi-core CPUs and a cluster. The parallel codes, implementing the master-slave model in C+MPI, differ in computation to communication ratios. The considered problems include: a genetic algorithm with various ratios of master processing time to communication...
-
Preconditioners with Low Memory Requirements for Higher-Order Finite-Element Method Applied to Solving Maxwell’s Equations on Multicore CPUs and GPUs
PublicationThis paper discusses two fast implementations of the conjugate gradient iterative method using a hierarchical multilevel preconditioner to solve the complex-valued, sparse systems obtained using the higher order finite-element method applied to the solution of the time-harmonic Maxwell equations. In the first implementation, denoted PCG-V, a classical V-cycle is applied and the system of equations on the lowest level is solved...
-
Superkomputer Tryton
Research EquipmentSuperkomputer o architekturze klastrowej
-
Optymalizacja wydajności obliczeniowej metody elementów skończonych w architekturze CUDA
PublicationCelem niniejszej rozprawy oraz stypendium odbytego w ramach projektu było opracowanie numerycznie efektywnego rozwiązania algorytmicznego i sprzętowego, które umożliwia przyspieszenie analizy problemów elektromagnetycznych metodą elementów skończonych (MES) z funkcjami bazowymi wysokiego rzędu. Metoda elementów skończonych w dziedzinie częstotliwości stanowi wydajne i uniwersalne narzędzie analizy układów mikrofalowych (rys....
-
Characterizing the Scalability of Graph Convolutional Networks on Intel® PIUMA
PublicationLarge-scale Graph Convolutional Network (GCN) inference on traditional CPU/GPU systems is challenging due to a large memory footprint, sparse computational patterns, and irregular memory accesses with poor locality. Intel’s Programmable Integrated Unffied Memory Architecture (PIUMA) is designed to address these challenges for graph analytics. In this paper, a detailed characterization of GCNs is presented using the Open-Graph Benchmark...
-
Electromagnetic Simulations with 3D FEM and Intel Optane Persistent Memory
PublicationAbstract—Intel Optane persistent memory has the potential to induce a change in how high-performance calculations requiring a large system memory capacity are conducted. This article presents what this change may look like in the case of factorization of large sparse matrices describing electromagnetic problems arising in the 3D FEM analysis of passive highfrequency components. In numerical tests, the Intel oneAPI MKL PARDISO was...
-
BENEFITS FROM BREAKING UP WITH LINUX NATIVE PACKET PROCESSING WHILE USING INTEL DPDK LIBRARIES
PublicationThe Intel Data Plane Development Kit (DPDK) is a set of libraries and drivers for fast packet processing in Linux. It is a dedicated framework for building efficient high-speed data plane applications supporting QoS features with poll mode drivers which are supporting virtual and physical NIC’s so environment can be used to build efficient data plane applications for packet networks. The results of test on Quality of Service Metering...
-
Paweł Czarnul dr hab. inż.
PeoplePaweł Czarnul obtained a D.Sc. degree in computer science in 2015, a Ph.D. in computer science granted by a council at the Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology in 2003. His research interests include:parallel and distributed processing including clusters, accelerators, coprocessors; distributed information systems; architectures of distributed systems; programming mobile devices....
-
Bogdan Pankiewicz dr hab. inż.
PeopleBogdan Pankiewicz graduated in 1993 from the Department of Electronics at Gdansk University of Technology (GUT) and in 2002 he obtained a doctoral degree in the field of electronics at the Faculty of Electronics, Telecommunications and Informatics at GUT. From the beginning of his career he is associated with GUT: first as an assistant (years 1994-2002) and then as assistant professor (since 2002) at the Faculty of Electronics,...
-
Marek Wójcikowski dr hab. inż.
PeopleMarek Wójcikowski graduated in 1993 from the Department of Electronics at Gdansk University of Technology (GUT). In 2002 he obtained a doctoral degree in the field of electronics and in 2016 he obtained a habilitation at the Faculty of Electronics, Telecommunications and Informatics at GUT. From the beginning of his career he is associated with GUT: first as an assistant (years 1994-2002) and then as assistant professor (since...
-
Jerzy Proficz dr hab. inż.
PeopleJerzy Proficz, Ph.D. is the director of the Centre of Informatics – Tricity Academic Supercomputer & networK (CI TASK) at Gdansk University of Technology, Poland. He earned his Ph.D. (2012) in HPC (High Performance Computing) in the subject of supercomputer resource provisioning and management for on-line data processing D.Sc. (2022) in the discipline: Information and Communication Technology. Author and co-author of over 50...
-
Implementacja w FPGA algorytmu detekcji krawędzi obrazu w czasie rzeczywistym
PublicationW artykule przedstawiono projekt architektury oraz implementację układową toru przetwarzania wstępnego obrazu z modułem detekcji krawędzi. Układ został zaimplementowany w FPGA Intel Cyclone. Zrealizowany moduł wykorzystuje pięć wybranych algorytmów wykrywania krawędzi, w tym Robertsa, Sobela i Prewitt.
-
Block-based Representation of Application Execution on Modern Parallel Systems
PublicationThe chapter presents how to model execution of a parallel computational application that is to be executed in a large-scale parallel or distributed environment with potentially thousands to millions of execution units. The representation uses pre- viously attributes and factors representative of modern high performance systems including multicore CPUs, GPUs, dedicated accelerators such as Intel Phi.
-
Józef Woźniak prof. dr hab. inż.
PeopleProfessor Józef Woźniak received his M.Sc., Ph.D. and D.Sc. degrees in electronics and telecommunications from the Faculty of Electronics, Gdańsk University of Technology (GUT), Poland, in 1971, 1976 and 1991, respectively. In January 2002 he became a full professor. In 1993 he was elected Associate Dean of the Faculty of Electronics and in 1994 he was he was appointed a Professor at GUT. Simultaneously, from October 1994 till...
-
Sprzętowa implementacja transformacji Hougha w czasie rzeczywistym
PublicationW artykule przedstawiono implementację sprzętową w FPGA algorytmu do wykrywania kształtów aproksymowanych zbiorem linii prostych podczas przetwarzania obrazu cyfrowego w czasie rzeczywistym. W opracowanej strukturze sprzętowej podniesiono efektywność przetwarzania poprzez zastosowanie przetwarzania przepływowego, lookup table, wykorzystanie wyłącznie arytmetyki liczb całkowitych oraz rozproszenie pamięci głosowania. Eksperymentalnie...
-
SEM images of Ni-Mo2CTx/Mo2Ga2C before and after catalytic dry reforming of methane
Open Research DataThe dataset includes SEM images of Ni-Mo2CTx/Mo2Ga2C catalysts before and after the dry reforming of methane.
-
SEM images of Ni-Mo2CTx/Mo3AlC2 before and after catalytic dry reforming of methane
Open Research DataThe dataset includes SEM images of Ni-Mo2CTx/Mo2Ga2C catalysts before and after the dry reforming of methane.
-
Optimal programming of critical sections in modern network processors under performance requirements.
PublicationPrzegląd konstrukcji i zastosowań metod programowania sekcji krytycznych w nowoczesnych procesorach sieciowych rodziny Intel IXP. Porównanie wydajnościowe w formie tabeli.
-
Karol Zdzisław Zalewski mgr inż.
People -
Programowanie w Asemblerze oraz Oprogramowanie Mikrokomputerów
e-Learning CoursesNauka podstaw programowania w asemblerze procesorów rodziny Intel 8086
-
A Task-Scheduling Approach for Efficient Sparse Symmetric Matrix-Vector Multiplication on a GPU
PublicationIn this paper, a task-scheduling approach to efficiently calculating sparse symmetric matrix-vector products and designed to run on Graphics Processing Units (GPUs) is presented. The main premise is that, for many sparse symmetric matrices occurring in common applications, it is possible to obtain significant reductions in memory usage and improvements in performance when the matrix is prepared in certain ways prior to computation....
-
Wykłady Otwarte TAJP
Events"Wymagania IoT na autonomicznych platformach mobilnych" – wykład dr. Marka Zmudy z Intel Technologies w ramach przedmiotu "Współczesne systemy elektroniki morskiej".
-
Wykłady Otwarte TAJP
EventsCyberbezpieczeństwo jednostek autonomicznych - wykład prowadzony przez dr. inż. Marka Zmudę z firmy Intel Technology Poland w ramach przedmiotu "Współczesne systemy elektroniki morskiej".
-
Playing the Sprint Retrospective
PublicationIn agile software development, where great emphasis is put on effective informal communication, success depends heavily on human and social factors. However, Scrum does not specify any techniques that aid the human side of software development. In this paper we investigate the use of 6 collaborative games for the Sprint Retrospective. Each game was implemented twice in a Scrum team in Intel Technology Poland. The received feedback...
-
KRICO Komponent rekomendacji dla inteligentnych chmur obliczeniowych
ProjectsProject realized in Academic Computer Centre TASK from 2014-06-10
-
Optimization of the System for Determining the Volume of Tissue Needed for Breast Reconstruction
PublicationThis article presents techniques for reconstructing surfaces and volume calculations using a point cloud generated from 3D imaging. The main objective of this article was to optimize the voxel size for the most accurate representation of the surface of the female breast. We experimented with different methods for determining volume using images from the Intel D435i camera. In addition, we designed application and measurement station...
-
3D-Breast System for Determining the Volume of Tissue Needed for Breast Reconstruction
Publication3D imaging systems can be used to effectively determine breast volumes for surgical applications. This article presents methods for surface reconstruction and volume determination based on the point cloud created by 3D imaging. Such a system would be used to accurately estimate breast volume in patients classified for breast reconstruction surgery at plastic surgery centers. To develop such a system, various methods of determining...
-
Superkomputery do wspomagania procesów gospodarczych ze szczególnym uwzględnieniem sektora bankowego
PublicationW artykule omówiono wykorzystanie superkomputerów do wspomagania procesów gospodarczych ze szczególnym uwzględnieniem sektora bankowego. Odniesiono się do wybranych projektów wspierających rozwój gospodarczy w oparciu o superkomputery. W szczególności zaproponowano zastosowanie HPC do implementacji wybranych metod sztucznej inteligencji w bankowości, w tym oceny ryzyka wybranych przedsięwzięć. Zaproponowane podejście umożliwia...
-
"3D-Breast System for Determining the Volume of Tissue Needed for Breast Reconstruction"
PublicationThis article presents methods for surface reconstruction and volume determination based on the point cloud created by 3D imaging. Such a system would be used to accurately estimate breast volume in patients classified for breast reconstruction surgery at plastic surgery centers. To develop such a system, various methods of determining volume, based on images from the Intel D435i camera, were tested. In addition, an application...
-
Zespolone techniki informatyczne w analizie struktury produkcji i wynikówekonomicznych dla korporacji przemysłu elektronicznego. Zamoj. Stud. i Ma-ter.**2003 z. 1 s. 109-116, 6 rys. 2 tab. bibliogr. 11 poz. Seria: Informatyka. Materiały z konferencji '' Informatyka w szkole''.
PublicationW artykule przeanalizowano strukturę produkcji oraz wyniki ekonomiczne czte-rech wiodących korporacji pzremysłu elektronicznego: Analog Devices, Intel,Texas Instruments i Motorola. Przy wykorzystaniu pakietu Microsoft Acces o-pracowana została baza danych zawierająca podstawowe informacje o korporac-jach. Zaproponowano i wykonano analizy porównawcze w zakresie finansowo-eko-nomicznym oraz przedstawiono przewidywania dotyczące...
-
Benchmarking Deep Neural Network Training Using Multi- and Many-Core Processors
PublicationIn the paper we provide thorough benchmarking of deep neural network (DNN) training on modern multi- and many-core Intel processors in order to assess performance differences for various deep learning as well as parallel computing parameters. We present performance of DNN training for Alexnet, Googlenet, Googlenet_v2 as well as Resnet_50 for various engines used by the deep learning framework, for various batch sizes. Furthermore,...
-
Taking advantage of the shared explicit cache system based critical sections in the shared memory parallel architectures
PublicationArtykuł prezentuje nową metodę implementacji sekcji krytycznych w równoległych architekturach z pamięcią współdzieloną, takich jak systemy zintegrowane wielowątkowe wieloprocesorowe. Metoda stanowi modyfikację i rozbudowanie metody zwanej Folding, dostępnej w procesorach sieciowych oraz jest w założeniach podobna do techniki zwanej cache-based locking. W porównaniu do dostępnych metod, nowa metoda usuwa problemy skalowalności i...