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Search results for: PIPELINED FFT PROCESSOR
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On simplification of residue scaling process in pipelined Radix-4 MQRNS FFT processor
PublicationResidue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent arithmetic overflow intermediate results after each butterfly have to be...
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On configuration of residue scaling process in pipelined radix-4 MQRNS FFT processor
PublicationResidue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and outputs four complex residue numbers. In order to prevent the arithmetic overflow in the succesive stage, every number has to be scaled,...
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Measurement of magnetic signals of vehicles with denoising by matched filtering with FPGA FFT processor
PublicationW artykule przedstawiono realizację systemu do analizy i identyfikacji pojazdów oparty na pomiarze indukcji magnetycznej. Proponowany system może być zastosowany do wykrywania i identyfikacji pojadów zawierających elementy ferromagnetyczne, które zaburzają pole magnetyczne ziemi. Zaburzenie to można zmierzyć przy zastosowaniu trójosiowych magnetometrów transduktorowych, pracującyh w układzie różnicowycm. Zastosowano w systemie...
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Analysis of magnetic signals of vehicles aided by matched filtering with FPGA FFT processor
PublicationW artykule przedstawiono system analizy i identyfikacji pojazdów oparty na pomiarze indukcji magnetycznej. Do tego celu jest stosowany zestaw czujników magnatycznych pracujących bezprzewodowo, który pozwala na monitorowanie ruchu pojazdów na lotniskach, w potrach i punktach kontroli granicznej. System taki może być zastosowany do wykrywania i identyfikacji pojadów zawierających elementy ferromagnetyczne, które zaburzają pole magnetyczne...
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Inrush and short circuit current identification based on real-time spectral analysis with the use of the FPGA FFT processor
PublicationW artykule przedstawiono krótkookresową analize widmową prądu załączeniowego i prądu zwarciowego transformatora w czasie rzeczywistym z zastosowaniem procesora FFT zrealizowanego w FPGA. Otrzymane widmo ułatwia rozróżnienie rodzaju prądu, co może być zastosowanei do lepszego sterowania zabezpieczneiem różnicowo-prądowym. Określono tez teoretyczne przebiegi prądów dla przyjetego modelu transformatora. Przeprowadzono ponadto analizę...
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Digital structures for high-speed signal processing
PublicationThe work covers several issues of realization of digital structures for pipelined processing of real and complex signals with the use of binary arithmetic and residue arithmetic. Basic rules of performing operations in residue arithmetic are presented along with selected residue number systems for processing of complex signals and computation of convolution. Subsequently, methods of conversion of numbers from weighted systems to...
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Pipelined Two-Operand Modular Adders
PublicationPipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The structure of pipelined TOMAs is usually obtained by inserting an appropriate number of pipeline register layers within...
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Shared processor scheduling
PublicationWe study the shared processor scheduling problem with a single shared processor to maximize total weighted overlap, where an overlap for a job is the amount of time it is processed on its private and shared processor in parallel. A polynomial-time optimization algorithm has been given for the problem with equal weights in the literature. This paper extends that result by showing an (log)-time optimization algorithm for a class...
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Acoustic Processor of the MCM Sonar
PublicationThis paper presents the concept of an acoustic processor of the mine countermeasure sonar. Developed at the Department of Marine Electronics Systems, Gdansk University of Technology, the acoustic processor is an element of the MG-89, a modernised underwater acoustic station. The focus of the article is on the modules of the processor. They are responsible for sampling analogue signals and implementing the algorithms controlling...
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Shared multi-processor scheduling
PublicationWe study shared multi-processor scheduling problem where each job can be executed on its private processor and simultaneously on one of many processors shared by all jobs in order to reduce the job’s completion time due to processing time overlap. The total weighted overlap of all jobs is to be maximized. The problem models subcontracting scheduling in supply chains and divisible load scheduling in computing. We show that synchronized...
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Acoustic Processor of the Mine Countermeasure Sonar
PublicationThis paper presents the concept of an acoustic processor of the mine countermeasure sonar. Developed at the Department of Marine Electronics Systems, Gdansk University of Technology, the acoustic processor is an element of the MG-89, an underwater acoustic station. The focus of the article is on the modules of the processor. They are responsible for sampling analogue signals and implementing the algorithms controlling the measurement...
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Pipelined division of signed numbers with the use of residue arithmetic in FPGA
PublicationAn architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length...
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Shared processor scheduling of multiprocessor jobs
PublicationWe study a problem of shared processor scheduling of multiprocessor weighted jobs. Each job can be executed on its private processor and simultaneously on possibly many processors shared by all jobs. This simultaneous execution reduces their completion times due to the processing time overlap. Each of the m shared processors may charge a different fee but otherwise the processors are identical. The goal is to maximize the total...
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Metoda szczególnego próbkowania a FFT w pomiarach elektroenergetycznych
PublicationW referacie przedstawiono podstawowe różnice pomiędzy metodami wykorzystującymi próbkowanie równomierne, a więc DFT i FFT a metodą szczególnego próbkowania, opracowaną specjalnie do pomiarów elektroenergetycznych, które wymagają dużej dokładności amplitudowej i fazowej ale ograniczonej liczby wyznaczanych harmonicznych.
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Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
PublicationIn this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algorithm based on segmentation of the divisor into two segments...
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Prediction of Processor Utilization for Real-Time Multimedia Stream Processing Tasks
PublicationUtilization of MPUs in a computing cluster node for multimedia stream processing is considered. Non-linear increase of processor utilization is described and a related class of algorithms for multimedia real-time processing tasks is defined. For such conditions, experiments measuring the processor utilization and output data loss were proposed and their results presented. A new formula for prediction of utilization was proposed...
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Fast implementation of FDTD-compatible green's function on multicore processor
PublicationIn this letter, numerically efficient implementation of the finite-difference time domain (FDTD)-compatible Green's function on a multicore processor is presented. Recently, closed-form expression of this discrete Green's function (DGF) was derived, which simplifies its application in the FDTD simulations of radiation and scattering problems. Unfortunately, the new DGF expression involves binomial coefficients, whose computations...
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Analog CMOS processor for early vision processing with highly reduced power consumption
PublicationA new approach to an analog ultra-low power visionchip design is presented. The prototype chip performs low-levelconvolutional image processing algorithms in real time. Thecircuit is implemented in 0.35 μm CMOS technology, contains64 x 64 SIMD matrix with embedded analogue processors APE(Analogue Processing Element). The photo-sensitive-matrix is of2.2 μm x 2.2 μm size, giving the density of 877 processors permm2. The matrix dissipates...
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High-speed fpga pipelined binary-to-residue converter
Publicationw pracy przedstawiono architekturę przepływowego konwertera z systemu z uzupełnieniem do 2 z systemu binarnego. zastosowano segmentację słowa wejściowego ze wstępną inwersją dla liczb ujemnych. reszty liczb reprezentowanych przez poszczególne segmenty są obliczane poprzez odczyt z pamięci adresowanej binarną reprezentacją segmentu. otrzymane reszty sumowane są w wielooperandowym sumatorze modulo z korekcją reszty dla liczb ujemnych.pracę...
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Analiza widmowa w czasie rzeczywistym prądów udarowych transformatora z zastosowaniem procesora FFT w technologii FPGA
PublicationW artykule przedstawiono krótkookresową analizę widmową prądu załączeniowego i prądu zwarciowego transformatora w czasie rzeczywistym z zastosowaniem procesora FFT zrealizowanego w FPGA. Określono tez teoretyczne przebiegi prądów dla przyjetego modelu transformatora. Przeprowadzono ponadto analizę wymagań związanych z obliczaniem prądu w czasie rzeczywistym.
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FFT spectrum based matching algorithm for activedynamic thermography
PublicationIn Active Dynamic thermography (ADT) sequences of consecutive temperature distributions are analyzed. In biomedical applications of ADT, the problems of a patient's movements in front of a thermal camera should be eliminated before data analysis. Complete mechanical stabilization of the patients is impossible due to natural voluntary and involuntary moves caused by pulse breathing, etc. This paper presents a simple and efficient...
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Comments on “Closed Form Variable Fractional Time Delay Using FFT”
PublicationIn this letter drawbacks of the aforementioned paper are pointed out. The proposed approach is improved with minor modifications of the discrete frequency response. This allows for design of fractional delay filters which are close to optimal and can be efficiently implemented in the frequency domain using the sliding DFT based structure. Alternatively, the derived equivalent closed form formulae for offset windows can be used...
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CMOS realisation of analogue processor for early vision processing
PublicationThe architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms ispresented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated usinga 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 framesper second, or achieve very low power...
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Hardware cryptography coprocessor for system on chip soft processor
PublicationW artykule przedstawiono realizację sprzętową i programową szyfrującejo i deszyfrującego algorytmu AES.Obydwie implementacje zostały zralizowane z wykorzystaniem układu Virtex II i przetestowane. Jako kryterium porónawcze wybrano zużycie zasobów układu oraz wydajność. Realizacja sprzętowa wykonuje operację szyfrowania 2 dekady szybcie niż wersja programowa, ale wymaga pięciokrotnie więcej zasobówIn this paper hardware and software...
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Procesing the complex signal in the acoustic processor of a sonobuoy system
PublicationW artykule przedstawiono metody cyfrowego przetwarzania sygnału kompleksowego w procesorze akustycznym systemu radiohydroboi. Omówiono ogólną postać systemu oraz sygnału kompleksowego. Opisano dwie alternatywne metody przetwarzania sygnału: pierwszą w dziedzinie czasu, drugą w dziedzinie częstotliwości. Zaprezentowano schematy blokowe algorytmów obu sposobów przetwarzania. Omówiono problemy praktycznej realizacji poszczególnych...
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Pipelined sceling of signed residue numbers with the mixed-radix conversion in the programmable gate array
PublicationIn this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System (MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue reprezentation of scaled terms, binary addition of these representations...
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Evolution-based scheduling of multiple variant and multiple processor programs
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An optimal abstraction model for hardware multithreding in modern processor architectures.
PublicationPrzegląd technologii implementacji wątków sprzętowych. Propozycja abstrakcji maszyny wirtualnej SIMD (On-Demand Virtual Single Instruction Multiple Data machine) do optymalnego użycia wątków sprzętowych.
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Implementation complexity analysis of the turbo decoding algorithms on digital signal processor
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Heavy stable charged particles search by novel pattern comparator processor
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Low Power Baseband Processor for M2M Reconfigurable Radio Test Platform
PublicationSoftware Defined Radio (SDR) is becoming more andmore frequently used technique for wireless communication. Itfacilitates as fast prototyping and is a versatile method fordeveloping new communication systems. SDR can be realizedbased on high computational capacity platform, where powerconsumption is no a primary concern like i.e. DVB or BTStransmitters. Another trend are low power systems, whereavailable power in reduced and more...
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Implementation of adaptive feed-forward algorithm on embedded PowerPC405 processor for FLASH accelerator
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Chromatic Scheduling of 1- and 2-Processor UET Tasks on Dedicated Machines with Availability Constraints
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Chromatic scheduling of 1- and 2-processor uet tasks on dedicated machines with availability constraints.
PublicationRozważono uogólnienie klasycznego szeregowania jednostkowych zadań jedno- i dwuprocesorowych na maszynach dedykowanych. Przyjęty model pozwala na naturalne wprowadzenie wszystkich klasycznych kryteriów optymalizacyjnych dla harmonogramów. Zaproponowano algorytmy wielomianowe dla systemów rzadkich.
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FFT analysis of temperature modulated semiconductor gas sensor response for the prediction of ammonia concentration under humidity interference
PublicationThe increasing environmental contamination forces the need to design reliable devices for detecting of the volatile compounds present in the air. For this purpose semiconductor gas sensors, which have been widely used for years, are often utilized. Although they have many advantages such as low price and quite long life time, they still lack of long term stability and selectivity. Namely, environmental conditions have significant...
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Determination of chlorine concentration using single temperature modulated semiconductor gas sensor
PublicationA periodic temperature modulation using sinusoidal heater voltage was applied to a commercial SnO2 semiconductor gas sensor. Resulting resistance response of the sensor was analyzed using a feature extraction method based on Fast Fourier Transformation (FFT). The amplitudes of the higher harmonics of the FFT from the dynamic nonlinear responses of measured gas were further utilized as an input for Artificial Neural...
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Hybridized Space-Vector Pulsewidth Modulation for Multiphase Two-Level Voltage Source Inverter
PublicationIn space vector pulsewidth modulation (SVPWM) algorithms for multiphase two-level voltage source inverters (VSI), the components of active vectors in all orthogonal spaces have to be calculated within the processor and stored in its memory. These necessitate intensive computational efforts of the processor and large memory space. This article presents a hybridized SVPWM for multiphase two-level VSI. In this algorithm, elements...
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Investigation of the temperature modulation parameters on semiconductor gas sensor response
PublicationIn this work we present the results of the investigation of the sensing properties of semiconductor gas sensors with a sinusoidally modulated temperature in the presence of synthetic air (SA) and three volatile air pollutants, i.e. NH3, NO2 and SO2. The measurements were performed for different average sensor heater temperatures and the amplitude of the modulation signal. In addition, the extraction of features from the sensor...
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Application of TMS320c67xx signal processors for SONIC-self-optimizing narrowband interference canceler
PublicationThe paper presents a laboratory system for testing active control algorithms of acoustics noise in ducts. An applied algorithm - self-optimizing narrowband interference canceller (SONIC), allows one to remove narrowband disturbances of constant or slowly time-varying frequencies. Example experimental results of using the laboratory system for supression of sinusoidal disturbance are described. An electronic part of the system was...
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Modeling Parallel Applications in the MERPSYS Environment
PublicationThe chapter presents how to model parallel computational applications for which simulation of execution in a large-scale parallel or distributed environment is performed within the MERPSYS environment. Specifically, it is shown what approaches can be adopted to model key paradigms often used for parallel applications: master-slave, geometric parallelism (single program multiple data), pipelined and divide-and-conquer applications....
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Process arrival pattern aware algorithms for acceleration of scatter and gather operations
PublicationImbalanced process arrival patterns (PAPs) are ubiquitous in many parallel and distributed systems, especially in HPC ones. The collective operations, e.g. in MPI, are designed for equal process arrival times (PATs), and are not optimized for deviations in their appearance. We propose eight new PAP-aware algorithms for the scatter and gather operations. They are binomial or linear tree adaptations introducing additional process...
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FPGA realization of an improved alpha max plus beta min algorithm
PublicationThe generalized improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. In case of four approximation regions it is possible to reduce the peak error form 3.95% to 0.33%. This...
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Acceleration of the discrete Green's function computations
PublicationResults of the acceleration of the 3-D discrete Green's function (DGF) computations on the multicore processor are presented. The code was developed in the multiple precision arithmetic with use of the OpenMP parallel programming interface. As a result, the speedup factor of three orders of magnitude compared to the previous implementation was obtained thus applicability of the DGF in FDTD simulations was significantly improved.
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Eksperymentalna weryfikacja przydatności wybranych parametrów standardu MPEG-7 w procesie klasyfikacji dźwięków instrumentów muzycznych
PublicationObecnie stosowane metody wyszukiwania informacji muzycznej w internecie bazują na parametrycznym opisie zawartości danych multimedialnych. W standardzie MPEG-7 w części dotyczącej sygnałów fonicznych zawarto opis oparty w dużej mierze o analizę widmową, przy czym dla dźwięków muzycznych parametryzowane jest widmo FFT fragmentu stanu quasi-ustalonego.
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The development of an underwater telephone for digital communication purposes
PublicationThe underwater telephone HTL-10 has been designed to provide voice and data communication between helicopter and submarines using acoustic waves. It works in a half-duplex mode and uses analogue power-efficient modulation in the form of a single side-band, suppressed carrier, in a wide range of frequencies. It generates the transmitted signal, and processes the received signals. It is implemented with the use of digital signal...
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Parallel immune system for graph coloring
PublicationThis paper presents a parallel artificial immune system designed forgraph coloring. The algorithm is based on the clonal selection principle. Each processor operates on its own pool of antibodies and amigration mechanism is used to allow processors to exchange information. Experimental results show that migration improves the performance of the algorithm. The experiments were performed using a high performance cluster on a set...
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Efektywny algorytm modelowania kanału radiokomunikacyjnego
PublicationW referacie omówiono efektywny algorytm modelowania kanału radiokomunikacyjnego z zanikami i propagacją wielodrogową. Zaproponowano szybką metodę ważonego próbkowania prążkowej odpowiedzi impulsowej kanału radiokomunikacyjnego. Przedstawiono algorytm generacji sekwencji współczynników rayleighowskich o pożądanym rozkładzie gęstości mocy z wykorzystaniem transformacji FFT. Na podstawie porównania ze stosowanym dotychczas modelem...
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Biophotonic low-coherence sensors with boron-doped diamond thin layer
PublicationLow-coherence sensors using Fabry-Perot interferometers are finding new applications in biophotonic sensing, especially due to the rapid technological advances in the development of new materials. In this paper we discuss the possibility of using boron-doped nanodiamond layers to protect mirror in a Fabry-Perot interferometer. A low-coherence sensor using Fabry-Perot interferometer with a boron-doped nanodiamond (B-NCD) thin protective...
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A filter bank solution for active power filter control algorithms
PublicationThb paper describes the proposed active power fiIter (APF) with a new control circuit based on an algorithm using ufilter bank and a harmonic predictor. The conirol circuit was realized using the digiiaI signor processor ADSP-21065L and FPGA circuiL In the proposed circuit transient performunee of APF is improved The active power fdter circuil has been built and teste6 and some illustrative, experimental results are uIso presented...
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THE SYNCHROSQUEEZING METHOD IN BEARING ESTIMATION OF STATIONARY SIGNALS FOR PASSIVE SONAR WITH TOWED ARRAY
PublicationIn this paper, a novel method of bearing estimation in a passive sonar system with a towed array is introduced. The classical approach of bearing estimation based on the spatial spectrum [1] is extended by using the synchrosqeezing method that is a part of the reassignment method introduced by Kodera et al. [2]. Using this method leads to a precise bearing estimation. The proposed method requires a relatively small amount of computation,...