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Search results for: BINARY/RESIDUE CONVERTER
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High-speed memoryless binary/residue converter
PublicationW pracy zaprezentowano nowy szybki konwerter z systemu binarnego do systemu resztowego dla liczb o zakresie do 60 bitów. W konwerterze stosowane są wyłącznie układy kombinacyjne. Algorytm konwertera oparty jest na dodawaniu niezerowych cyfr binarnych reprezentacji kolejnych potęg 2 modulo m. Dodawanie jest realizowane przy użyciu wielooperandowego sumatora CSA oraz sumatora CPA. Suma wyjściowa CPA jest redukowana do zakresu 2m-1...
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Effective residue-to-binary converter with the Chinese Remainder Theorem
PublicationKonwersja liczb z systemu resztowego do systemu binarnego jest podstawową operacją we wszystkich układach cyfrowego przetwarzania sygnałów, które wykorzystują system resztowy. W niniejszej pracy zaproponowano nową metodę konwersji opartą o chińskie twierdzenie o resztach dla modułów 5- i 6-bitowych. Specyficzną cechą nowej metody jest sposób obliczania tzw. współczynnika nadmiaru w formule chińskiego twierdzenia o resztach, co...
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High-speed binary-to-residue converter with improved architecture.
PublicationPrzedstawiono ulepszoną architekturę szybkiego konwertera liczb z systemu binarnego do systemu resztowego dla liczb ze znakiem w kodzie U2. Algorytm konwertera oparty jest o segmentację słowa wejsciowego nasegmenty 4-bitowe. Reszty liczb reprezentowanych przez segmenty sąobliczane poprzez odwzorowanie. Wielooperandowe sumowanie modulo jest realizowane przy użyciu drzewa Wallace'a z segmentacją wektorów wyjściowych oraz finalnego...
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FPGA realization of the high-speed binary-to-residue converter
Publicationprzedstawiono architekturę i realizację w technologii fpga konwertera z systemu binarnego do systemu resztowego. algorytm konwertera oparty jest na podziale słowa wejściowego na segmenty 4-bitowe i następnie obliczeniu reszty liczby reprezentowanej przez dany segment, sumowaniu binarnym przy zastosowaniu csa i redukcji modulo w układzie dwuoperandowego sumatora modulo.
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High-speed fpga pipelined binary-to-residue converter
Publicationw pracy przedstawiono architekturę przepływowego konwertera z systemu z uzupełnieniem do 2 z systemu binarnego. zastosowano segmentację słowa wejściowego ze wstępną inwersją dla liczb ujemnych. reszty liczb reprezentowanych przez poszczególne segmenty są obliczane poprzez odczyt z pamięci adresowanej binarną reprezentacją segmentu. otrzymane reszty sumowane są w wielooperandowym sumatorze modulo z korekcją reszty dla liczb ujemnych.pracę...
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High-speed residue-to-binary converter based on the Chinese RemainderTheorem.
PublicationPrzedstawiono szybki konwerter z systemu resztowego do systemu binarnego dla modułów 5-bitowych oparty o chińskie twierdzenie o resztach. Projekcje ortogonalne są generowane przy użyciu odwzorowania realizowanego przy zastosowaniu funkcji logicznych pięciu zmiennych. Wartość wyjściowa jest obliczana przy użyciu drzewaWallace'a z segmentacją wektorów wyjściowych i redukcją do 2M, M zakres liczbowy systemu oraz efektywny finalny...
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High-speed binary-to-residue converter with the reduced input layer
Publicationprzedstawiono architekturę szybkiego konwertera z systemu binarnego do systemu resztowego dla modułów 5-bitowych. Algorytm konwersji oparty jest na dodawaniu binarnym reszt potęg liczby 2 obliczonych modulo m i redukcji modulo m sumy dla poszczególnych modułów bazy systemu resztowego. Warstwa wejciowa konwertera jest redukowana poprzez wykorzystanie wspólnych elementów układu dla odpowiednio zestawionych par modułów.
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An improved high-speed residue-to-binary converter based on the chinese remainder theorem
Publicationw pracy zaprezentowano nowy szybki konwerter z systemu resztowego do systemu binarnego. Projekcje ortogonalne wyznaczane są przy użyciu funkcji logicznych pięciu zmiennych. Suma projekcji obliczana jest z zastosowaniem drzewa Wallace'a. Wektor sumy i wektor przeniesienia są dzielone na segmenty tak aby liczba reprezentowana łącznie przez obydwa segmenty o młodszych wagach nie przekraczała zakresu systemu resztowego,M. Bity segmentów...
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FPGA realization of the high-speed residue-to-binary converter based on the Chinese Remainder Theorem
Publication...
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FPGA realization of the high-speed residue-to-binary converter based on chinese remainder theorem
PublicationW pracy przedstawiono architekturę, realizację FPGA oraz symulację numeryczną na poziomie bitowym szybkiego konwertera z systemu resztowego do systemu binarnego dla modułów 5-bitowych opartego na chińskim twierdzeniu o resztach. Algorytm konwertera obejmuje obliczanie projekcji ortogonalnych poprzez odczyt pamięci oraz sumowanie modulo M realizowane dwustopniowo, pierwszy stopień oparty o sumatory CSA umożliwia redukcję do zakresu...
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High-Speed Binary-to-Residue Converter Design Using 2-Bit Segmentation of the Input Word
PublicationIn this paper a new approach to the design of the high-speed binary-to-residue converter is proposed that allows the attaining of high pipelining rates by eliminating memories used in modulo m generators. The converter algorithm uses segmentation of the input binary word into 2-bit segments. The use and effects of the input word segmentation for the synthesis of converters for five-bit moduli are presented. For the number represented...
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Residue-to-two's complement converter based on core function
PublicationW artykule przedstawiono układową realizację konwertera z systemu resztowego do systemu binarnego bazującego na funkcji jądra. Zastosowanie funkcji jądra powoduje zmniejszenie wymagań sprzętowych przy realizacji konwertera. W publikacji omówiono problem dektekcji znaku oraz realizacje ukłądową konwertera w środowisku FPGA.
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Digital structures for high-speed signal processing
PublicationThe work covers several issues of realization of digital structures for pipelined processing of real and complex signals with the use of binary arithmetic and residue arithmetic. Basic rules of performing operations in residue arithmetic are presented along with selected residue number systems for processing of complex signals and computation of convolution. Subsequently, methods of conversion of numbers from weighted systems to...
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Pipelined division of signed numbers with the use of residue arithmetic in FPGA
PublicationAn architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length...
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Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
PublicationIn this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algorithm based on segmentation of the divisor into two segments...
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RNS/TCS CONVERTER DESIGN USING HIGH-LEVEL SYNTHESIS IN FPGA
PublicationAn experimental high-level synthesis (HLS) of the residue number system (RNS) to two’s-complement system (TCS) converter in the Vivado Xilinx FPGA environment is shown. The assumed approach makes use of the Chinese Remainder Theorem I (CRT I). The HLS simplifies and accelerates the design and implementation process, moreover the HLS synthesized architecture requires less hardware by about 20% but the operational frequency is smaller...
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HIGH LEVEL SYNTHESIS IN FPGA OF TCS/RNS CONVERTER
PublicationThe work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is...
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Pipelined sceling of signed residue numbers with the mixed-radix conversion in the programmable gate array
PublicationIn this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System (MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue reprezentation of scaled terms, binary addition of these representations...
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Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection
PublicationA scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues...
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Pipelined Two-Operand Modular Adders
PublicationPipelined two-operand modular adder (TOMA) is one of basic components used in digital signal processing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The structure of pipelined TOMAs is usually obtained by inserting an appropriate number of pipeline register layers within...
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Single-Slope ADC With Embedded Convolution Filter for Global-Shutter CMOS Image Sensors
PublicationThis brief presents an analog-to-digital converter (ADC) suitable for acquisition and processing of images in the global-shutter mode at the pixel level. The ADC consists of an analog comparator, a multi-directional shift register for the comparator states, and a 16-bit reversible binary counter with programmable step size. It works in the traditional single-slope mode. The novelty is that during each step of the reference ramp,...
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Discrete convolution based on polynomial residue representation
PublicationThis paper presents the study of fast discrete convolution calculation with use of the Polynomial Residue Number System (PRNS). Convolution can be based the algorithm similar to polynomial multiplication. The residue arithmetic allows for fast realization of multiplication and addition, which are the most important arithmetic operations in the implementation of convolution. The practical aspects of hardware realization of PRNS...
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Revalorization of the Szewalski binary vapour cycle
PublicationThe aim of the paper is to revalorizate of the Szewalski binary vapour cycle by analysing thermodynamical and operational parameters of this cycle. This was carried by accessible numerical CFM (Computational Flow Mechanics) codes type, by step-by-step modeling of separates apparatus. The binary vapour cycle is providing steam as the working fluid in the high temperature part of the cycle, while another fluid - a low boiling point...
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Implementation of discrete convolution using polynomial residue representation
PublicationConvolution is one of the main algorithms performed in the digital signal processing. The algorithm is similar to polynomial multiplication and very intensive computationally. This paper presents a new convolution algorithm based on the Polynomial Residue Number System (PRNS). The use of the PRNS allows to decompose the computation problem and thereby reduce the number of multiplications. The algorithm has been implemented in Xilinx...
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Exergy Losses in the Szewalski Binary Vapor Cycle
PublicationIn this publication, we present an energy and exergy analysis of the Szewalski binary vapor cycle based on a model of a supercritical steam power plant. We used energy analysis to conduct a preliminary optimization of the cycle. Exergy loss analysis was employed to perform a comparison of heat-transfer processes, which are essential for hierarchical cycles. The Szewalski binary vapor cycle consists of a steam cycle bottomed with...
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Chromogenic azomacrocycles with imidazole residue: Structure vs. properties
PublicationNew diazo macrocycles linked by hydrocarbon chain bearing imidazole or 4-methylimidazole residue have been synthetized with satisfactory yield (24–55%). The structure of macrocycles was confirmed by X-ray analysis and spectroscopic methods (1H NMR, MS, FTIR). Metal cation complexation studies were carried out in acetonitrile and acetonitrile-water system. It was found that azomacrocyles form triple-decker complexes with lead(II)....
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On simplification of residue scaling process in pipelined Radix-4 MQRNS FFT processor
PublicationResidue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent arithmetic overflow intermediate results after each butterfly have to be...
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Control strategy for the multilevel cascaded H-bridge converter
PublicationThe paper presents the control strategy for Cascaded H-bridge (CHB) converter . The converter output voltage using Space-Vector Pulse Width Modulation (SV-PWM) strategy is controlled. The DC-link voltages are controlled by appropriate choice of H-Bridges and appropriate choice of active and passive vectors.
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On configuration of residue scaling process in pipelined radix-4 MQRNS FFT processor
PublicationResidue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and outputs four complex residue numbers. In order to prevent the arithmetic overflow in the succesive stage, every number has to be scaled,...
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Wideband Modeling of DC-DC Buck Converter with GaN Transistors
PublicationThe general wideband modeling method of the power converter is presented on the example of DC-DC buck converter with GaN High Electron Mobility Transistors (HEMT). The models of all basic and parasitic components are briefly described. The two methods of Printed Circuit Board (PCB) layout parameter extraction are presented. The results of simulation in Saber@Sketch simulation software and measurements are compared. Next, the model...
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Conjugated control of triple active bridge converter with common HFT
PublicationPaper presents synthetic analyses of single input, dual output DC/AC/DC converter with common high frequency transformer. Rise the problem of cross-coupling power flows between secondary terminals, under asymmetrical control operating condition. It also proposes a new approach to converter control, based on conjugated phase shift modulation and defines its limitations. Finally, the developed control technique was verified by simulation...
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Prediction of ringing frequencies in DC-DC boost converter
PublicationIn the paper ringing phenomena in a DC-DC boost converter is presented. The ringing frequency is calculated using an analytical formula. The necessary wide band models of MOSFET transistor, passive and parasitics are described. The calculation results are verified in simulation and laboratory tests.
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Scaling of numbers in residue arithmetic with the flexible selection of scaling factor
PublicationA scaling technique of numbers in resudue arithmetic with the flexible selection of the scaling factor is presented. The required scaling factor can be selected from the set of moduli products of the Residue Number System (RNS) base. By permutation of moduli of the number system base it is possible to create many auxilliary Mixed-Radix Systems associated with the given RNS with respect to the base, but they have different sets...
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Cascaded Buck Hybrid Interlink Converter for Multiple-Input / Multiple-Output Operation
PublicationThe provision of isolated- and non-isolated DC output voltages by Power electronics power-conditioning devices in the recent ‘green-energy-revolution’ era is on course. In this paper, a structure for multi-input multi-output(MIMO) DC–DC buck converter is proposed to generate output voltages of varying levels with fewer component-count. The DC output voltage of each of the constituting buck converters can be used independently or...
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Novel Diazocrowns with Pyrrole Residue as Lead(II) Colorimetric Probes
PublicationNovel 18- and 23-membered diazomacrocycles were obtained with satisfactory yields by diazocoupling of aromatic diamines with pyrrole in reactions carried under high dilution conditions. X-ray structure of macrocycle bearing five carbon atoms linkage was determined and described. Compounds were characterized as chromogenic heavy metal ions receptors. Selective color and spectral response for lead(II) was found in acetonitrile and...
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Dynamic variables limitation for backstepping control of induction machine and voltage source converter
PublicationDynamic variables limitation for backstepping control of induction machine and voltage source converter The paper presents the method of control of an induction squirrel-cage machine supplied by a voltage source converter. The presented idea is based on an innovative method of the voltage source converter control, consisting in direct joining of the motor control system with the voltage source rectifier control system. The combined...
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Electromagnetic interference frequencies prediction model of flyback converter for snubber design
PublicationSnubber design for flyback converters usually requires experimental prototype measurements or simulation based on accurate and complex models. In this study simplified circuit modelling of a flyback converter has been described to dimension snubbers in early stage of design process. Simulation based prediction of the transistor and diode ringing frequencies has been validated by measurements in a prototype setup. In that way obtained...
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Electron-impact ionization of fluoromethanes – Review of experiments and binary-encounter models
PublicationExperiments and recommended data on electron-impact ionization of methane and fluoromethanes (CH3F, CH2F2, CHF3, CF4) are reviewed and compared with binary-encounter models (Gryzinski’s, ´ Deutsch and Märk’s, and Kim and Rudd’s). A good agreement between recent experiments and the two latter classical-like models is shown. Kim and Rudd’s model (calculated presently in the restricted HartreeFock 6-31**G orbital basis) predicts well...
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Non-isolated resonant quasi-Z-source network DC–DC converter
PublicationA novel non-isolated resonant quasi-impedance (quasi-Z)-source network DC–DC converter is proposed. The resonant impedance source network is derived from the quasi-Z-source network by including the autotransformer-based resonant cell instead of the second inductor of the quasi-Z-network. The leakage inductance of the autotransformer and two resonant capacitors connected in series with the autotransformer windings constitute a high-frequency...
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Power converter interface for urban DC traction substations - solutions and functionality.
PublicationThis paper focuses on extending an urban DC traction substation functionality by means of an additional power converter interface (PCI). In particular, by enabling bidirectional energy exchange between LV DC traction grid, AC grid and V2G chargers. Among other things, the presented material compares general attributes of the most promising DC/DC converters that can be used in a PCI, meet the requirements of galvanic isolation and...
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Binary-Encounter Model for Direct Ionization of Molecules by Positron-Impact
PublicationWe introduce two models for the computation of direct ionization cross sections by positron impact over a wide range of collision energies. The models are based on the binary-encounter-Bethe model and take into account an extension of the Wannier theory. The cross sections computed with these models show good agreement with experimental data. The extensions improve the agreement between theory and experiment for collision energies...
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Predicting sulfanilamide solubility in the binary mixtures using a reference solvent approach
PublicationBackground. Solubility is a fundamental physicochemical property of active pharmaceutical ingredients. The optimization of a dissolution medium aims not only to increase solubility and other aspects are to be included such as environmental impact, toxicity degree, availability, and costs. Obtaining comprehensive...
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Thermodynamic Characteristics of Phenacetin in Solid State and Saturated Solutions in Several Neat and Binary Solvents
PublicationThe thermodynamic properties of phenacetin in solid state and in saturated conditions in neat and binary solvents were characterized based on differential scanning calorimetry and spectroscopic solubility measurements. The temperature-related heat capacity values measured for both the solid and melt states were provided and used for precise determination of the values for ideal solubility, fusion thermodynamic functions, and...
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Systematic approach to binary classification of images in video streams using shifting time windows
Publicationin the paper, after pointing out of realistic recordings and classifications of their frames, we propose a new shifting time window approach for improving binary classifications. We consider image classification in tewo steps. in the first one the well known binary classification algorithms are used for each image separately. In the second step the results of the previous step mare analysed in relatively short sequences of consecutive...
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Lossless Compression of Binary Trees with Correlated Vertex Names
PublicationCompression schemes for advanced data structures have become the challenge of today. Information theory has traditionally dealt with conventional data such as text, image, or video. In contrast, most data available today is multitype and context-dependent. To meet this challenge, we have recently initiated a systematic study of advanced data structures such as unlabeled graphs [1]. In this paper, we continue this program by considering...
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Accurate modeling of layout parasitic to forecast EMI emitted from a DC-DC converter.
PublicationThis paper illustrates how to account for all parasitic due to the layout of a power converter (inductive and capacitive), in order to forecast electromagnetic interferences (EMI). The method is generic, and is validated here in the simple example of a DC-DC converter, realized on different technologies: insulated metal substrate (IMS), printed circuit board (PCB). In addition, several layouts aspects will be investigated. Conclusions...
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Binary Mixtures of Selected Bisphenols in the Environment: Their Toxicity in Relationship to Individual Constituents
PublicationBisphenol A (BPA) is one of the most popular and commonly used plasticizer in the industry. Over the past decade, new chemicals that belong to the bisphenol group have increasingly been used in industrial applications as alternatives to BPA. Nevertheless, information on the combined effects of bisphenol (BP) analogues is insufficient. Therefore, our current study aimed to find the biological response modulations induced by the...
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Production of Biogas from Distillation Residue as a Waste Material from the Distillery Industry in Poland
PublicationIn this paper, the possibility to obtain an alternative source of energy from methane fermentation, catalysed by biomass, has been discussed in detail. As a main substrate, the distillation residue from the distillery industry was taken in the case of mono-fermentation and its co-fermentation with sewage sludge. The results showed that higher biogas and methane production can be obtained in a mono-fermentation process. Fermentation...
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A low-voltage CMOS negative impedance converter for analogue filtering applications
PublicationLow-voltage high-frequency continuous-time filters are still required in many applications and are the subject of continuing research. There are many techniques to realize integrated filters, including OTA C, Opamp RC and MOSFET-C-Opamp. The latter two show high dynamic range at low supply voltage, but their frequency operating range is usually limited to several megahertz. Transconductance filters are dedicated to higher frequencies....
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Ferromagnetism in Pr-rich binary Pr7Ru3 intermetallic compound
PublicationWe present the synthesis and experimental characterization of the binary intermetallic compound Pr7Ru3. The polycrystalline sample was prepared by arc melting pure Pr and Ru, followed by homogenization at 500 °C and 600 °C for 48 and 89 h, respectively. Powder x-ray diffraction confirms that Pr7Ru3 crystallizes in an orthorhombic crystal structure (Pnma, space group no. 62) with the lattice parameters: a = 7.3606(7) Å, b = 23.120(1)...