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Search results for: FPGA, ASIC, DESIGN AND VERIFICATION, PROTOTYPING
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ASIC Design Example of Complex SoC with FPGA Prototyping
PublicationThe paper presents an example of the System on a Chip design, where the FPGA prototyping has been used. Two FPGA prototypes have been realized. The first FPGA prototype uses AVNET board containing Xilinx Virtex4 device accompanied by custom board with required devices. The second FPGA prototype has been built using the custom PCB with Xilinx Virtex-4 XC4VLX60 FPGA accompanied by all needed external components. The final system...
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ASIC Design Example of Complex SoC with FPGA Prototyping
PublicationThe paper presents an example of the System on a Chip design, where the FPGA prototyping has been used. Two FPGA prototypes have been realized. The first FPGA prototype uses AVNET board containing Xilinx Virtex4 device accompanied by custom board with required devices. The second FPGA prototype has been built using the custom PCB with Xilinx Virtex-4 XC4VLX60 FPGA accompanied by all needed external components. The final system...
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FPGA and ASIC implementation of the algorithm for traffic monitoring in urban areas
PublicationW artykule przedstawiono algorytm detekcji obrazu oraz jego realizację sprzętową w technikach FPGA i ASIC. Algorytm ten dedykowany jest do detekcji ruchu pojazdów i jest realizowany w czasie rzeczywistym. Użyto pojedynczą, umieszczoną na stałe kamerę monochromatyczną o niskiej rozdzielczości. Wykonywane są również operacje eliminacji cieni i rozjaśnień obrazu. Nachodzenie obiektów na siebie nie jest brane pod uwagę. Realizacja...
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Hardware-Software Implementation of a Sensor Network for CityTraffic Monitoring Using the FPGA- and ASIC-Based Sensor Nodes
PublicationArtykuł opisuje prototypową sieć sensorową do monitorowania ruchu pojazdów w mieście. Węzły sieci sensorowej, wyposażone w kamerę o niskiej rozdzielczości, obserwują ulice i wykrywają poruszające się obiekty. Detekcja obiektów jest realizowana w oparciu o własny algorytm segmentacji obrazów, wykorzystujący podwójne odejmowanie tła, wykrywanie krawędzi i cieni, działający na dedykowanym systemie mikroelektronicznym typu ''System...
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Verification and Benchmarking in MPA Coprocessor Design Process
PublicationThis paper presents verification and benchmarking required for the development of a coprocessor digital circuit for integer multiple-precision arithmetic (MPA). Its code is developed, with the use of very high speed integrated circuit hardware description language (VHDL), as an intellectual property core. Therefore, it can be used by a final user within their own computing system based on field-programmable gate arrays (FPGAs)....
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Bogdan Pankiewicz dr hab. inż.
PeopleBogdan Pankiewicz graduated in 1993 from the Department of Electronics at Gdansk University of Technology (GUT) and in 2002 he obtained a doctoral degree in the field of electronics at the Faculty of Electronics, Telecommunications and Informatics at GUT. From the beginning of his career he is associated with GUT: first as an assistant (years 1994-2002) and then as assistant professor (since 2002) at the Faculty of Electronics,...
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Design of versatile ASIC and protocol tester for CBM readout system
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RNS/TCS CONVERTER DESIGN USING HIGH-LEVEL SYNTHESIS IN FPGA
PublicationAn experimental high-level synthesis (HLS) of the residue number system (RNS) to two’s-complement system (TCS) converter in the Vivado Xilinx FPGA environment is shown. The assumed approach makes use of the Chinese Remainder Theorem I (CRT I). The HLS simplifies and accelerates the design and implementation process, moreover the HLS synthesized architecture requires less hardware by about 20% but the operational frequency is smaller...
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Marek Wójcikowski dr hab. inż.
PeopleMarek Wójcikowski graduated in 1993 from the Department of Electronics at Gdansk University of Technology (GUT). In 2002 he obtained a doctoral degree in the field of electronics and in 2016 he obtained a habilitation at the Faculty of Electronics, Telecommunications and Informatics at GUT. From the beginning of his career he is associated with GUT: first as an assistant (years 1994-2002) and then as assistant professor (since...
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Design and realization of two-operand modular adders in the FPGA
PublicationW pracy zaprezentowano strukturę sumatorów modularnych w środowisku Xilinx z użyciem rodziny układów Virtex-6. Rozważono dwa typy sumatorów, jeden dla modułów 5-bitowych i drugi dla 6-bitowych. Zaprojektowano ich struktury i podano eksperymentalne wyniki implementacji.
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System do prototypowania bezprzewodowych inteligentnych urządzeń monitoringu audio-video
PublicationW komunikacie przedstawiono system prototypowania bezprzewodowych urządzeń do monitoringu audio-video. System bazuje na układach FPGA Virtex6 i wielu dodatkowych wspierających urządzeniach jak: szybka pamięć DDR3, mała kamera HD, mikrofon z konwerterem A/C, moduł radiowy WiFi, itp. Funkcjonalność systemu została szczegółowo opisana w komunikacie. System został zoptymalizowany do pracy pod kontrolą systemu operacyjnego Linux, zostały...
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Design and experimental verification of multi-layer waveguide using pin/hole structure
PublicationThis study presents a novel technique for minimizing RF leakage in metallic hollow waveguides fabricated using the multilayer split-block method. By integrating a pin/hole wall into the split-block multilayers, a substantial reduction of RF leakage can be achieved while reducing the circuit size and mitigating the performance variations. To validate the proposed approach, a slot antenna fed by single ridge waveguide has been prototyped...
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The new footbridge in city of Cracow dynamic design and final verification in test loading
PublicationArtykuł przedstawia rozwój projektu kładki od formy architektonicznej do ostatecznego kształtu konstrukcji.
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Cyfrowy akcelerator wybranych modułów standardu kompresji wideo H.264
PublicationW artykule przedstawiono konfigurowalny cyfrowy akcelerator estymacji ruchu przeznaczony dla enkodera wideo standardu H.264. Akcelerator został zaimplementowany w technologii FPGA oraz w układzie ASIC w technologii UMC 90 nm. Obie implementacje zostały zweryfikowane, a szczegółowe wyniki pomiarów akceleratora ASIC zostały porównane z innymi dostępnymi w literaturze propozycjami. System został zoptymalizowany do współpracy z oprogramowaniem...
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Design and Simulation Verification of Low Power Wireless Charging Battery System for Electric Bicycle
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Cyfrowy akcelerator wybranych modułów standardu kompresji wideo H.264
PublicationW komunikacie przedstawiono konfigurowalny cyfrowy akcelerator estymacji ruchu (motion estimation) przeznaczony dla enkodera wideo standardu H.264. Akcelerator został wstępnie zaimplementowany w układzie FPGA VIRTEX6-VLX365T, a następnie w układzie ASIC w technologii UMC 90 nm. Obie implementacje zostały zweryfikowane pozytywnie, a szczegółowe wyniki symulacji i pomiarów akceleratora ASIC zostały porównane z innymi dostępnymi w...
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<title>Design and simulation of FPGA implementation of a RF control system for the TESLA test facility</title>
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<title>FPGA-based TESLA cavity SIMCON DOOCS server design, implementation, and application</title>
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The methodology of design of axial clearances compensation unit in hydraulic satellite displacement machine and their experimental verification
PublicationA new methodology of calculating the dimensions of the axial clearance compensation unit in the hydraulic satellite displacement machine is described in this paper. The methods of shaping the compensation unit were also proposed and described. These methods were used to calculate the geometrical dimensions of the compensation field in an innovative prototype of a satellite hydraulic motor. This motor is characterized by the fact...
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Akcelerator transformacji DCT do kompresji obrazu w sensorach wizyjnych
PublicationW komunikacie przedstawiono konfigurowalny cyfrowy akcelerator transformacji DCT przeznaczony dla enkodera wideo standardu H.264. Akcelerator realizuje także odwrotnątransformacjęDCT oraz kwantyzacjęi dekwantyzację. Akcelerator początkowo zaimplementowano w układzie FPGA. Zostałon pomyślnie zweryfikowany, a następnie zaimplementowany w układzie ASIC w technologii UMC 90 nm. Szczegółowe wyniki testów akceleratora ASIC zostały...
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Akcelerator predykcji wewnątrzramkowej H.264 do kompresji obrazu w sensorach wizyjnych
PublicationW artykule przedstawiono konfigurowalny cyfrowy akcelerator predykcji wewnątrzramkowej przeznaczony dla enkodera wideo standardu H.264. Akcelerator realizuje predykcję typu „intra” dla makrobloków luminancji o wymiarach 4x4 i 16x16. Akcelerator wstępnie zaimplementowano w układzie FPGA, gdzie został on pomyślnie zweryfikowany, a następnie zaimplementowano go w układzie ASIC w technologii UMC 90 nm. Szczegółowe wyniki testów akceleratora...
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Akcelerator predykcji wewnątrzramkowej H.264 do kompresji obrazu w sensorach wizyjnych
PublicationW komunikacie przedstawiono konfigurowalny cyfrowy akcelerator predykcji wewnątrzramkowej przeznaczony dla enkodera wideo standardu H.264. Akcelerator realizuje predykcję typu „intra” dla makrobloków luminancji o wymiarach 4x4 i 16x16. Akcelerator wstępnie zaimplementowano w układzie FPGA, gdzie został on pomyślnie zweryfikowany, a następnie zaimplementowano go w układzie ASIC w technologii UMC 90 nm. Szczegółowe wyniki testów...
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Potential of Polish R&D industry in the context of prototyping, design, development and control of a dedicated national satellite SAR system for marine ecosystem monitoring. Technical paper - preliminary study
Publicationpace technology is currently one of the most important elements in the advance of information societies and knowledge-based economies all over the world. The European Space Agency (ESA) is in the focal point of European space activities, while the European Union provides strong financial support for the development of space technologies and applications in its flagship programs. In a domestic scope, the Polish Space Agency (POLSA)...
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FIReWORK: FIR Filters Hardware Structures Auto-Generator
PublicationThe paper presents application called FIReWORK, that allows for automatic creation of the VHDL hardware structures of FIR filters. Automat- ically generated specialized hardware solutions dedicated to the FPGA and ASIC are commonly known as Intellectual Property Cores. The essential fu- ture of the application is easy initialization of FIR filter parameters in GUI, and then automatically design, calculate and generate the IP Core...
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Hip endhoprothesis development using rapid prototyping methods
PublicationIntegrated product development based on Rapid Prototyping methods, connected with computer aided 3D design and computer aided engineering enables fast and full new product verification and validation. A case study derived from clinical and technological practice using hip implant construction is also included.
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Implementation of multi-operand addition in FPGA using high-level synthesis
PublicationThe paper presents the results of high-level synthesis (HLS) of multi-operand adders in FPGA using the Vivado Xilinx environment. The aim was to estimate the hardware amount and latency of adders described in C-code. The main task of the presented experiments was to compare the implementations of the carry-save adder (CSA) type multi-operand adders obtained as the effect of the HLS synthesis and those based on the basic component...
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Forum on Specification and Design Languages (Forum on Specification, Verification and Design Languages)
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COMPARISON OF SYSTEM ON CHIP TECHNOLOGIES FOR SPACE APPLICATIONS
PublicationThe paper presents a review of technologies available for the implementation of digital and mixed signal systems, particularly the system on a chip (SoC) for space applications. The phenomena encountered in the space environment are briefly presented, together with the known solutions, regarding the design of complex electronic systems. The most important norms regarding single die integrated circuits designed for space are also...
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Akcelerator transformacji DCT do kompresji obrazu w sensorach wizyjnych
PublicationW komunikacie przedstawiono konfigurowalny cyfrowyakcelerator transformacji DCT przeznaczony dla enkodera wideo standardu H.264. Akcelerator realizuje także odwrotnątransformacjęDCT oraz kwantyzację i dekwantyzację. Akcelerator początkowo zaimplementowano w układzie FPGA. Został on pomyślnie zweryfikowany, a następnie zaimplementowany w układzie ASIC w technologiiUMC 90 nm. Szczegółowe wyniki testów akceleratora ASIC zostały...
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Jerzy Konorski dr hab. inż.
PeopleJerzy Konorski received his M. Sc. degree in telecommunications from Gdansk University of Technology, Poland, and his Ph. D. degree in computer science from the Polish Academy of Sciences, Warsaw, Poland. In 2007, he defended his D. Sc. thesis at the Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology. He has authored over 150 papers, led scientific projects funded by the European Union,...
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Natalia Stawicka-Morawska dr inż.
PeopleMgr inż. Natalia Stawicka-Morawska pracuje na Politechnice Gdańskiej od października 2017 r. na stanowisku Asystenta, na Wydziale Inżynierii Mechanicznej i Okrętownictwa (poprzednio: Wydziale Mechanicznym), w Instytucie Mechaniki i Konstrukcji Maszyn (poprzednio: Katedrze Mechaniki i Mechatroniki).Prowadzona przez nią działalność naukowa dotyczy dziedziny nauk technicznych w dyscyplinie naukowej budowa i eksploatacja maszyn. Główną...
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Interactive Prototypes in Teaching User-Centred Design and Business Process Modelling
PublicationThis publication describes experiences gathered during the use of interactive prototyping in two areas: design of user interfaces for a touch screen information kiosk and interactive prototyping of business processes. Prototyping is promoted here as a technique useful for both visualizing design concepts and for stimulating communication within relevant teams. Developing interactive prototypes of use interfaces is discussed here...
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FPGA-Based System for Electromagnetic Interference Evaluation in Random Modulated DC/DC Converters
PublicationField-Programmable Gate Array (FPGA) provides the possibility to design new “electromagnetic compatibility (EMC) friendly” control techniques for power electronic converters. Such control techniques use pseudo-random modulators (RanM) to control the converter switches. However, some issues connected with the FPGA-based design of RanM, such as matching the range of fixed-point numbers, might be challenging. The modern programming...
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Przegląd metod szybkiego prototypowania algorytmów uczenia maszynowego w FPGA
PublicationW artykule opisano możliwe do wykorzystania otwarte narzędzia wspomagające szybkie prototypowanie algorytmów uczenia maszynowego (ML) i sztucznej inteligencji (AI) przy użyciu współczesnych platform FPGA. Przedstawiono przykład szybkiej ścieżki przy realizacji toru wideo wraz z implementacją przykładowego algorytmu prze-twarzania w trybie na żywo.
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Konferencja ORConf 2018
EventsORConf to konferencja na temat projektowania układów cyfrowych oraz systemów wbudowanych typu "open source", obejmująca obszary elektroniki od poziomu tranzystora po system Linux i nie tylko.
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Mechatronic design o strongly nonlinear systems on a basis of three wheeled mobile platform
PublicationRemarkable grow in demand both of mobile platform operability performance and reduction of project leading time development encourage to apply modern algorithms and reliable engineering tools for the design process. The paper discusses the mechatronic design applied for the surveillance system based on the energy performance index algorithm. The exploited mechatronic techniques i.e. virtual prototyping, Hardware-In-the-Loop Simulation...
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HIGH LEVEL SYNTHESIS IN FPGA OF TCS/RNS CONVERTER
PublicationThe work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is...
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Realizacja algorytmów szyfrowania symetrycznego w układach FPGA Xilinx Virtex II.
PublicationW pracy zaprezentowano realizację algorytmów szyfrowania symetrycznego w układach FPGA firmy Xilinx z najnowszej rodziny Virtex II. Podkreślono zalety użycia układów programowalnych w systemach kryptograficznych w stosunku do układów ASIC oraz rozwiązań programowych. Przedstawiono struktury szyfrów blokowych Rijndael, Serpent i Twofish oraz moduły składowe i sposób ich realizacji w układach FPGA. Porównano architektury przetwarzania...
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Design and implementation principles of FIReWORK ONLINE - the VHDL autogenerator for hardware structures
PublicationThe paper presents an aspects of remote autogeneration of hardware structures. The solution is an online application, that is running on the server side and allows to design a particular filters and other selected hardware and generate its structure in the form of VHDL, dedicated to FPGA design environments. The paper also addresses the problem of parameterization of algorithms used to generate the hardware structures and current...
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The project IDENT: Multimodal biometric system for bank client identity verification
PublicationBiometric identity verification methods are implemented inside a real banking environment comprising: dynamic handwritten signature verification, face recognition, bank cli-ent voice recognition and hand vein distribution verification. A secure communication system based on an intra-bank client-server architecture was designed for this purpose. Hitherto achieved progress within the project is reported in this paper with a focus...
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Optimization of clamping stiffness during milling of high-dimensional structures with the use of techniques of experiment – aided virtual prototyping
PublicationThe subject of this paper is a method of searching for conditions of minimizing the vibration level of a tool-high dimensional flexible workpiece, at unchangeable technological parameters of the machining process. It depends on repeatable change of the values of the stiffness coefficients as soon as an optimal vibration state of the workpiece approaches. There are assessed the values of dominant ”peaks” in the frequency spectra...
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Intelligent PI controller and its application to dissolved oxygen tracking problem
PublicationThe paper addresses design, calibration, implementation and simulation of the intelligent PI controller used for dissolved oxygen (DO) tracking in wastewater treatment plant (WWTP). The calibration process presented in this paper utilizes both engineering and scientific methods. Verification of the control system design method was obtained via simulation experiments.
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Recent and Emerging Applications of Graphene-based metamaterials in Electromagnetics
PublicationSurface Plasmon Polaritons (SPPs) operating in mid-infrared up to terahertz (THz) frequencies have been traditionally manufactured on expensive metals such as gold, silver, etc. However, such metals have poor surface confinement that limits the optical applications of SPPs. The invention of graphene is a breakthrough in plasmon-based devices in terms of design, fabrication and applications, thanks to its plasmonic wave distribution,...
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Mechatronics design, modelling and controlling of the Stewart-Gough platform
PublicationThis paper presents a mechatronics design of a low cost Stewart-Gough platform (SGP) with rotary actuators. The designed SGP is supposed to be applied in a ball & plate control system. The synthesis of the ball & plate control system is also within the subject of the paper. A mechatronics design process of the SGP was conducted with computer-aided design (CAD) software. Unique analytical solutions of an inverse kinematics problem...
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Rule-Based Model for Selecting Integration Technologies for Smart Cities Systems
PublicationThe aim of this article is to present the stages of development for an information technology integration model for the design of systems for smart cities. The Introduction explains the need for integration technologies and presents a model for selecting integration technologies and the conditions for its use in designing smart cities systems. Then two verification stages of the presented model are discussed. In the first stage,...
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Digital structures for high-speed signal processing
PublicationThe work covers several issues of realization of digital structures for pipelined processing of real and complex signals with the use of binary arithmetic and residue arithmetic. Basic rules of performing operations in residue arithmetic are presented along with selected residue number systems for processing of complex signals and computation of convolution. Subsequently, methods of conversion of numbers from weighted systems to...
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Computer-Aided Greenery Design—Prototype Green Structure Improving Human Health in Urban Ecosystem
PublicationIncreasing population and urbanization, with climate change consequences, such as rising temperatures, influence public health and well-being. The search to improve the quality of life in cities becomes one of the priority objectives. A solution can be found in the role of greenery in an urban environment and its impact on human health. This opens a path toward experimentation on microclimate green structures that can be inserted...
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CFD and FEM model of an underwater vehicle propeller
PublicationDuring the project execution of design and optimization the Remotely Operated Vehicle (ROV) research on its propulsion has been carried out. The entire project was supported by CFD and FEM calculations, which taking into account the characteristics of underwater vehicle. One of the tasks was to optimize the semi-open duct for horizontal propellers, which provided propulsion and controllability in horizontal plane. In order to...
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Analysis of economical lighting of highways in the environment of SMOL language
PublicationThe paper puts forward and implements a method of designing and creating a modelling simulation environment for eztensive and complete analysis of economical lighting on highways. From a general design viewpoint, the proposed solution explores the concept of a network description language (SMOL), which has been designed to describe the necessary network functions, mechanisms, and devices; for the purpose of their computer simulation...
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Experiment-aided virtual prototyping to minimize tool-workpiece vibration during boring of large-sized structures
PublicationThe paper presents the author's method of solving the problems of vi-bration suppression during boring of large-sized workpieces by means of an in-novative method of adjusting the rotational speed of the boring bar. It consists in selecting the spindle speed in accordance with the results of the cutting process simulation. The method includes identification of the model of the finite element method of the boring bar. The Root Mean...